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Rajendra Bishnoi
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Evaluation of hybrid memory technologies using SOT-MRAM for on-chip cache hierarchy
F Oboril, R Bishnoi, M Ebrahimi, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
1822015
Ultra-fast and high-reliability SOT-MRAM: From cache replacement to normally-off computing
G Prenat, K Jabeur, P Vanhauwaert, G Di Pendina, F Oboril, R Bishnoi, ...
IEEE Transactions on Multi-Scale Computing Systems 2 (1), 49-60, 2015
1712015
Read disturb fault detection in STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 International Test Conference, 1-7, 2014
812014
Avoiding unnecessary write operations in STT-MRAM for low power implementation
R Bishnoi, F Oboril, M Ebrahimi, MB Tahoori
Fifteenth International Symposium on Quality Electronic Design, 548-553, 2014
692014
Improving Write Performance for STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, M Tahoori
IEEE Transaction on Magnetics 52 (8), 1-11, 2016
652016
Layout-based modeling and mitigation of multiple event transients
M Ebrahimi, H Asadi, R Bishnoi, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
562015
Architectural aspects in design and analysis of SOT-based memories
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 700-707, 2014
562014
Design of defect and fault-tolerant nonvolatile spintronic flip-flops
R Bishnoi, F Oboril, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016
512016
Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
442014
Inkjet-printed EGFET-based physical unclonable function—Design, evaluation, and fabrication
AT Erozan, GC Marques, MS Golanbari, R Bishnoi, S Dehm, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
332018
Self-timed read and write operations in STT-MRAM
R Bishnoi, F Oboril, M Ebrahimi, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015
312015
Defect injection, fault modeling and test algorithm generation methodology for STT-MRAM
SM Nair, R Bishnoi, MB Tahoori, G Tshagharyan, H Grigoryan, ...
2018 IEEE International Test Conference (ITC), 1-10, 2018
302018
A cross-layer adaptive approach for performance and power optimization in STT-MRAM
N Sayed, R Bishnoi, F Oboril, MB Tahoori
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 791-796, 2018
262018
A survey of test and reliability solutions for magnetic random access memories
P Girard, Y Cheng, A Virazel, W Zhao, R Bishnoi, MB Tahoori
Proceedings of the IEEE 109 (2), 149-169, 2020
242020
Non-volatile non-shadow flip-flop using spin orbit torque for efficient normally-off computing
R Bishnoi, F Oboril, MB Tahoori
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 769-774, 2016
242016
Opportunistic write for fast and reliable STT-MRAM
N Sayed, M Ebrahimi, R Bishnoi, MB Tahoori
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
212017
A spintronics memory PUF for resilience against cloning counterfeit
SB Dodo, R Bishnoi, SM Nair, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019
192019
VAET-STT: Variation aware STT-MRAM analysis and design space exploration tool
SM Nair, R Bishnoi, MS Golanbari, F Oboril, F Hameed, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
192017
Exploiting STT-MRAM for approximate computing
N Sayed, F Oboril, A Shirvanian, R Bishnoi, MB Tahoori
2017 22nd IEEE European Test Symposium (ETS), 1-6, 2017
192017
A cross-layer analysis of soft error, aging and process variation in near threshold computing
A Gebregiorgis, S Kiamehr, F Oboril, R Bishnoi, MB Tahoori
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 205-210, 2016
182016
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