| Frequency improvement of systolic array-based CNNs on FPGAs J Zhang, W Zhang, G Luo, X Wei, Y Liang, J Cong 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019 | 41 | 2019 |
| An efficient mapping approach to large-scale dnns on multi-fpga architectures W Zhang, J Zhang, M Shen, G Luo, N Xiao 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 39 | 2019 |
| A fast and low computation consumption model for system-level thermal management in 3D IC Y Pi, N Wang, J Zhang, W Wang, G Luo, M Miao, W Xu, Y Jin 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1933-1939, 2016 | 12 | 2016 |
| Formulating data-arrival synchronizers in integer linear programming for cgra mapping Y Guo, J Wang, J Zhang, G Luo 2021 58th ACM/IEEE Design Automation Conference (DAC), 943-948, 2021 | 11 | 2021 |
| Pasgcn: An reram-based pim design for gcn with adaptively sparsified graphs T Yang, D Li, F Ma, Z Song, Y Zhao, J Zhang, F Liu, L Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 6 | 2022 |
| Enhanced fast Boolean matching based on sensitivity signatures pruning J Zhang, L Ni, S Zheng, H Liu, X Zou, F Wang, G Luo 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 5 | 2021 |
| STAR: Synthesis of stateful logic in RRAM targeting high area utilization F Wang, G Luo, G Sun, J Zhang, J Kang, Y Wang, D Niu, H Zheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 5 | 2020 |
| An FPGA-based neural network overlay for ADAS supporting multi-model and multi-mode J Zhang, T Yang, Q Li, B Zhou, Y Yang, G Luo, J Shi 2021 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2021 | 4 | 2021 |
| Parallel stateful logic in RRAM: Theoretical analysis and arithmetic design F Wang, G Luo, G Sun, J Zhang, P Huang, J Kang 2019 IEEE 30th International Conference on Application-specific Systems …, 2019 | 4 | 2019 |
| Efficient super-resolution system with block-wise hybridization and quantized winograd on fpga B Shi, J Zhang, Z He, X Wei, S Li, G Luo, H Zheng, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 3 | 2023 |
| Dual-output LUT merging during FPGA technology mapping F Wang, L Zhu, J Zhang, L Li, Y Zhang, G Luo Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 3 | 2020 |
| Adaptive-Precision Framework for SGD Using Deep Q-Learning W Zhang, H Huang, J Zhang, M Jiang, G Luo 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 3 | 2018 |
| Search space reduction for the non-exact projective NPNP Boolean matching problem F Wang, J Zhang, L Wu, W Zhang, G Luo 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 3 | 2017 |
| Scaling up physical design: Challenges and opportunities G Luo, W Zhang, J Zhang, J Cong Proceedings of the 2016 on International Symposium on Physical Design, 131-137, 2016 | 3 | 2016 |
| GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs X Wei, J Zhang, G Luo 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 2 | 2023 |
| Automated design of chiplets A Sangiovanni-Vincentelli, Z Liang, Z Zhou, J Zhang Proceedings of the 2023 International Symposium on Physical Design, 1-8, 2023 | 2 | 2023 |
| Easymac: Design exploration-enabled multiplier-accumulator generator using a canonical architectural representation J Zhang, Q Gao, Y Guo, B Shi, G Luo 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 647-653, 2022 | 2 | 2022 |
| Rethinking npn classification from face and point characteristics of boolean functions J Zhang, S Zheng, L Ni, H Li, G Luo 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 1 | 2023 |
| Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks Y Guo, X Wei, J Zhang, G Luo 2022 IEEE 40th International Conference on Computer Design (ICCD), 385-393, 2022 | 1 | 2022 |
| PowerSyn: A Logic Synthesis Framework With Early Power Optimization S Zou, J Zhang, B Shi, G Luo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | | 2023 |
Guojie LuoPeking UniversityVerified email at pku.edu.cn
