| A systematic methodology for characterizing scalability of DNN accelerators using SCALE-sim A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 67 | 2020 |
| Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs JM Joseph, C Blochwitz, A García-Ortiz, T Pionteck Microprocessors and Microsystems 48, 36-47, 2017 | 16 | 2017 |
| A cycle-accurate network-on-chip simulator with support for abstract task graph modeling JM Joseph, T Pionteck 2014 International Symposium on System-on-Chip (SoC), 1-6, 2014 | 11 | 2014 |
| NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures JM Joseph, L Bamberg, D Ermel, BR Perjikolaei, A Drewes, A García-Ortiz, ... IEEE Access 7, 135145-135163, 2019 | 10 | 2019 |
| An FPGA-based prototyping framework for Networks-on-Chip T Drewes, JM Joseph, T Pionteck 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 10 | 2017 |
| A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip JM Joseph, S Wrieden, C Blochwitz, A García-Oritz, T Pionteck 2016 11th International Symposium on Reconfigurable Communication-centric …, 2016 | 9 | 2016 |
| Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs JM Joseph, L Bamberg, I Hajjar, BR Perjikolaei, A García-Ortiz, T Pionteck ACM Transactions on Modeling and Computer Simulation (TOMACS) 32 (1), 1-21, 2021 | 8* | 2021 |
| Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models D Passaretti, JM Joseph, T Pionteck 2019 International Conference on Field-Programmable Technology (ICFPT), 279-282, 2019 | 7 | 2019 |
| Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels L Bamberg, JM Joseph, R Schmidt, T Pionteck, A García-Ortiz 2018 28th International Symposium on Power and Timing Modeling, Optimization …, 2018 | 7 | 2018 |
| Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS JM Joseph, M Mey, K Ehlers, C Blochwitz, T Winker, T Pionteck 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 7 | 2017 |
| Adaptive allocation of default router paths in Network-on-Chips for latency reduction JM Joseph, C Blochwitz, T Pionteck 2016 International Conference on High Performance Computing & Simulation …, 2016 | 7 | 2016 |
| Hardware-Accelerated radix-tree based string sorting for big data applications C Blochwitz, J Wolff, JM Joseph, S Werner, D Heinrich, S Groppe, ... Architecture of Computing Systems-ARCS 2017: 30th International Conference …, 2017 | 6 | 2017 |
| An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases C Blochwitz, JM Joseph, R Backasch, T Pionteck, S Werner, D Heinrich, ... 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 6 | 2015 |
| Optimising operator sets for analytical database processing on FPGAs A Drewes, JM Joseph, B Gurumurthy, D Broneske, G Saake, T Pionteck Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2020 | 4 | 2020 |
| Simulation environment for link energy estimation in networks-on-chip with virtual channels JM Joseph, L Bamberg, I Hajjar, R Schmidt, T Pionteck, A Garcia-Ortiz Integration 68, 147-156, 2019 | 4 | 2019 |
| Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs JM Joseph, L Bamberg, G Krell, I Hajjar, A Garcia-Oritz, T Pionteck 2018 13th International Symposium on Reconfigurable Communication-centric …, 2018 | 3 | 2018 |
| Design method for asymmetric 3D interconnect architectures with high level models JM Joseph, L Bamberg, S Wrieden, D Ermel, A Garcia-Oritz, T Pionteck 2017 12th International Symposium on Reconfigurable Communication-centric …, 2017 | 3 | 2017 |
| An optimized radix-tree for hardware-accelerated index generation for Semantic Web Databases C Blochwitz, JM Joseph, T Pionteck, R Backasch, S Werner, D Heinrich, ... International Conference on ReConFigurable Computing and FPGAs (ReConFig …, 2015 | 3 | 2015 |
| Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs JM Joseph, C Blochwitz, T Pionteck, A García-Ortiz 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP …, 2015 | 3 | 2015 |
| NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories F Staudigl, H Al Indari, D Schön, D Sisejkovic, F Merchant, JM Joseph, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 2 | 2022 |
Lennart BambergPrincipal Processor Architect @ NXPBestätigte E-Mail-Adresse bei uni-bremen.de
