| Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing PR Chidambaram, C Bowen, S Chakravarthi, C Machala, R Wise IEEE Transactions on Electron Devices 53 (5), 944-964, 2006 | 257 | 2006 |
| Transistor fabrication methods using dual sidewall spacers H Bu, PR Chidambaram, R Khamankar, L Hall US Patent 7,217,626, 2007 | 248 | 2007 |
| 35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS PR Chidambaram, BA Smith, LH Hall, H Bu, S Chakravarthi, Y Kim, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 48-49, 2004 | 153 | 2004 |
| Forming a retrograde well in a transistor to enhance performance of the transistor S Chakravarthi, PR Chidambaram, RC Bowen, H Bu US Patent 7,061,058, 2006 | 124 | 2006 |
| A thermodynamic criterion to predict wettability at metal-alumina interfaces PR Chidambaram, GR Edwards, DL Olson Metallurgical Transactions B 23, 215-222, 1992 | 113 | 1992 |
| Fabrication of abrupt ultra-shallow junctions S Chakravarthi, P Chidambaram US Patent 6,852,603, 2005 | 100 | 2005 |
| Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel PR Chidambaram US Patent 7,208,362, 2007 | 90 | 2007 |
| A comparison of the wettability of copper-copper oxide and silver-copper oxide on polycrystalline alumina AM Meier, PR Chidambaram, GR Edwards Journal of Materials Science 30, 4781-4786, 1995 | 71 | 1995 |
| Increased drive current by isotropic recess etch PR Chidambaram, L Hall, H Bu US Patent 7,060,579, 2006 | 70 | 2006 |
| Recess etch for epitaxial SiGe S Chakravarthi, P Chidambaram, J Weijtmans US Patent 7,553,717, 2009 | 57 | 2009 |
| Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS CH Choi, PR Chidambaram, R Khamankar, CF Machala, Z Yu, RW Dutton IEEE Transactions on Electron Devices 49 (7), 1227-1231, 2002 | 54 | 2002 |
| Pattern based prediction for plasma etch KO Abrokwah, PR Chidambaram, DS Boning IEEE transactions on semiconductor manufacturing 20 (2), 77-86, 2007 | 50 | 2007 |
| Gate length dependent polysilicon depletion effects CH Choi, PR Chidambaram, R Khamankar, CF Machala, Z Yu, RW Dutton IEEE Electron Device Letters 23 (4), 224-226, 2002 | 49 | 2002 |
| Carbon-Doped Epitaxial SiGe S Chakravarthi, P Chidambaram, J Weijtmans US Patent App. 11/693,552, 2008 | 44 | 2008 |
| Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant PR Chidambaram, A Chatterjee, S Chakravarthi US Patent 6,682,980, 2004 | 44 | 2004 |
| Methods, systems and structures for forming improved transistors PR Chidambaram, H Bu US Patent 7,122,435, 2006 | 42 | 2006 |
| Comparative analysis of semiconductor device architectures for 5-nm node and beyond P Feng, SC Song, G Nallapati, J Zhu, J Bao, V Moroz, M Choi, XW Lin, ... IEEE Electron Device Letters 38 (12), 1657-1660, 2017 | 40 | 2017 |
| Probing nanoscale local lattice strains in advanced Si complementary metal-oxide-semiconductor devices J Huang, MJ Kim, PR Chidambaram, RB Irwin, PJ Jones, JW Weijtmans, ... Applied physics letters 89 (6), 2006 | 40 | 2006 |
| Phosphorus Activated NMOS Using SiC Process S Chakravarthi, PR Chidambaram US Patent App. 12/364,772, 2011 | 38* | 2011 |
| Modelling of the spreading kinetics of reactive brazing alloys on ceramic substrates: copper–titanium alloys on polycrystalline alumina A Meier, PR Chidambaram, GR Edwards Acta materialia 46 (12), 4453-4467, 1998 | 37 | 1998 |
