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Saurabh Adya
Saurabh Adya
Apple
Bestätigte E-Mail-Adresse bei umich.edu
Titel
Zitiert von
Zitiert von
Jahr
Fixed-outline floorplanning: Enabling hierarchical design
SN Adya, IL Markov
IEEE Transactions on very large scale Integration (VLSI) systems 11 (6 …, 2003
4602003
Fixed-outline floorplanning: Enabling hierarchical design
SN Adya, IL Markov
IEEE Transactions on very large scale Integration (VLSI) systems 11 (6 …, 2003
4602003
Capo: robust and scalable open-source min-cut floorplacer
JA Roy, DA Papa, SN Adya, HH Chan, AN Ng, JF Lu, IL Markov
Proceedings of the 2005 international symposium on Physical design, 224-226, 2005
1812005
Fixed-outline floorplanning through better local search
SN Adya, IL Markov
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in …, 2001
1532001
Consistent placement of macro-blocks using floorplanning and standard-cell placement
SN Adya, IL Markov
Proceedings of the 2002 international symposium on Physical design, 12-17, 2002
1502002
Min-cut floorplacement
JA Roy, SN Adya, DA Papa, IL Markov
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1462006
Unification of partitioning, placement and floorplanning
SN Adya, S Chaturvedi, JA Roy, DA Papa, IL Markov
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
1432004
Benchmarking for large-scale placement and beyond
SN Adya, MC Yildiz, IL Markov, PG Villarrubia, PN Parakh, PH Madden
Proceedings of the 2003 international symposium on Physical design, 95-103, 2003
982003
On whitespace and stability in mixed-size placement and physical synthesis
SN Adya, IL Markov, PG Villarrubia
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
772003
Combinatorial techniques for mixed-size placement
SN Adya, IL Markov
ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (1 …, 2005
622005
Unification of partitioning, floorplanning and placement
SN Adya, S Chaturvedi, JA Roy, DA Papa, IL Markov
Proc. ICCAD, 550-557, 2004
612004
Are floorplan representations important in digital design?
HH Chan, SN Adya, IL Markov
Proceedings of the 2005 international symposium on physical design, 129-136, 2005
602005
On whitespace in mixed-size placement and physical synthesis
SN Adya, IL Markov, PG Villarrubia
Proc. Int. Conf. on Computer Aided Design, 311-318, 2003
222003
On whitespace and stability in physical synthesis
SN Adya, IL Markov, PG Villarrubia
Integration 39 (4), 340-362, 2006
202006
Hybrid Transformer/CTC networks for hardware efficient voice triggering
S Adya, V Garg, S Sigtia, P Simha, C Dhir
arXiv preprint arXiv:2008.02323, 2020
192020
Methods and apparatuses for circuit design and optimization
S Adya, KS McElvain, G Paul
US Patent 8,307,315, 2012
182012
Methods and apparatuses for circuit design and optimization
S Adya, KS McElvain, G Paul
US Patent 8,307,315, 2012
182012
Constructive benchmarking for placement
DA Papa, SN Adya, IL Markov
Proceedings of the 14th ACM Great Lakes symposium on VLSI, 113-118, 2004
162004
Improving min-cut placement for VLSI using analytical techniques
SN Adya, IL Markov, PG Villarrubia
Proc. IBM ACAS Conference, 55-62, 2003
162003
An effective timing-driven detailed placement algorithm for FPGAs
S Dhar, MA Iyer, S Adya, L Singhal, N Rubanov, DZ Pan
Proceedings of the 2017 ACM on International Symposium on Physical Design …, 2017
132017
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