An 8.5 mW Continuous-Time Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR JG Kauffman, P Witte, J Becker, M Ortmanns
IEEE Journal of Solid-State Circuits 46 (12), 2869-2881, 2011
108 2011 A 72 dB DR, CT ΔΣ modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz Bw JG Kauffman, P Witte, M Lehmann, J Becker, Y Manoli, M Ortmanns
IEEE Journal of Solid-State Circuits 49 (2), 392-404, 2013
75 2013 A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW P Witte, JG Kauffman, J Becker, Y Manoli, M Ortmanns
2012 IEEE International Solid-State Circuits Conference, 154-156, 2012
59 2012 An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization JG Kauffman, P Witte, J Becker, M Ortmanns
2011 IEEE International Solid-State Circuits Conference, 472-474, 2011
50 2011 Background DAC error estimation using a pseudo random noise based correlation technique for sigma-delta analog-to-digital converters P Witte, M Ortmanns
IEEE Transactions on Circuits and Systems I: regular papers 57 (7), 1500-1512, 2010
43 2010 A correlation-based background error estimation technique for bandpass Delta–Sigma ADC DACs P Witte, JG Kauffman, J Becker, M Ortmanns
IEEE Transactions on Circuits and Systems II: Express Briefs 58 (11), 748-752, 2011
9 2011 A background DAC error estimation in Sigma-Delta ADCs using a pseudo random noise based correlation technique P Witte, M Ortmanns
2009 IEEE International Symposium on Circuits and Systems, 1549-1552, 2009
9 2009 Estimating Ultimate Recovery and Economic Analysis of Shale Oil Wells in Eagle Ford and Bakken Q Darugar, D Heinisch, BJ Lundy, P Witte, W Wu, S Zhou
Abu Dhabi International Petroleum Exhibition & Conference, 2016
8 2016 Method and structure for domino read bit line and set reset latch YH Chan, RM Houle, R Sautter, P Witte
US Patent App. 12/053,128, 2008
8 2008 Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs P Witte, C Noeske, M Ortmanns
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
6 2010 Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry D Franger, R Sautter, T Werner, P Witte
US Patent App. 12/060,537, 2008
4 2008 Performance and area optimization using sequential flexibility C Albrecht, P Witte, A Kuehlmann
Proc. International Workshop on Logic and Synthesis, 2004
4 2004 Method and System for Modifying and Presenting Document Data J Fenkes, G Hellner, T Warner, P Witte
US Patent App. 11/689,555, 2008
3 2008 A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs PW Jesko Flemming, Bernhard Wicht
IEEE International Symposium on Circuits and Systems (ISCAS), 2023
1 2023 A digital background correction for DAC nonlinearities in lowpass and bandpass delta–sigma modulators—Theory and implementation P Witte, J Kauffman, J Becker, M Ortmanns
Proc. 9th Int. Conf. Sampling Theory Appl., 2011
1 2011 Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures PW Jesko Flemming, Bernhard Wicht
2023 International Conference on Synthesis, Modeling, Analysis and …, 2023
2023 Correlation Based Nonlinearity Estimation and Background Correction for Delta-sigma Analog-to-digital Converters P Witte
Institut für Mikroelektronik, 2014
2014 An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal P Witte, JG Kauffman, T Brückner, J Becker, M Ortmanns
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 73-76, 2012
2012 method for generating a scan chain in a custom electronic circuit design D Franger, P Witte, A Windschiegl
US Patent App. 11/850,704, 2009
2009 Scan chain in a custom electronic circuit design D Franger, P Witte, A Windschiegl
US Patent App. 11/850,709, 2008
2008