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Julien Schmaltz
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Inference and abstraction of the biometric passport
F Aarts, J Schmaltz, F Vaandrager
International Symposium On Leveraging Applications of Formal Methods …, 2010
1122010
On conformance testing for timed systems
J Schmaltz, J Tretmans
International Conference on Formal Modeling and Analysis of Timed Systems …, 2008
942008
Analysis of a clock synchronization protocol for wireless sensor networks
F Heidarian, J Schmaltz, F Vaandrager
International Symposium on Formal Methods, 516-531, 2009
802009
A generic model for formally verifying noc communication architectures: A case study
D Borrione, A Helmy, L Pierre, J Schmaltz
First International Symposium on Networks-on-Chip (NOCS'07), 127-136, 2007
502007
Formal API specification of the PikeOS separation kernel
F Verbeek, O Havle, J Schmaltz, S Tverdyshev, H Blasum, B Langenstein, ...
NASA Formal Methods: 7th International Symposium, NFM 2015, Pasadena, CA …, 2015
392015
A decision procedure for deadlock-free routing in wormhole networks
F Verbeek, J Schmaltz
IEEE transactions on parallel and distributed systems 25 (8), 1935-1944, 2013
39*2013
A functional formalization of on chip communications
J Schmaltz, D Borrione
Formal Aspects of Computing 20 (3), 241-258, 2008
38*2008
Hunting deadlocks efficiently in microarchitectural models of communication fabrics
F Verbeek, J Schmaltz
2011 Formal Methods in Computer-Aided Design (FMCAD), 223-231, 2011
372011
A formal approach to the verification of networks on chip
D Borrione, A Helmy, L Pierre, J Schmaltz
EURASIP Journal on Embedded Systems 2009, 1-14, 2009
372009
Model-based testing of electronic passports
WI Mostowski, E Poll, J Schmaltz, J Tretmans, RJM Wichers Schreur
Berlin: Springer Verlag, 2009
362009
On necessary and sufficient conditions for deadlock-free routing in wormhole networks
F Verbeek, J Schmaltz
IEEE Transactions on Parallel and Distributed Systems 22 (12), 2022-2032, 2011
352011
A formal model of clock domain crossing and automated verification of time-triggered hardware
J Schmaltz
Formal Methods in Computer Aided Design, 2007. FMCAD'07, 223-230, 2007
35*2007
Towards a formal theory of on chip communications in the ACL2 logic
J Schmaltz, D Borrione
Proceedings of the sixth international workshop on the ACL2 theorem prover …, 2006
292006
A functional approach to the formal specification of networks on chip
J Schmaltz, D Borrione
Formal Methods in Computer-Aided Design, 52-66, 2004
272004
A generic network on chip model
J Schmaltz, D Borrione
International Conference on Theorem Proving in Higher Order Logics, 310-325, 2005
252005
Formal specification of networks-on-chips: deadlock and evacuation
F Verbeek, J Schmaltz
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
242010
A conformance testing relation for symbolic timed automata
S Von Styp, H Bohnenkamp, J Schmaltz
Formal Modeling and Analysis of Timed Systems: 8th International Conference …, 2010
222010
A comment on "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks”
F Verbeek, J Schmaltz
Parallel and Distributed Systems, IEEE Transactions on 22 (10), 1775-1776, 2011
192011
The axiomatization of override and update
J Berendsen, DN Jansen, J Schmaltz, FW Vaandrager
Journal of Applied Logic 8 (1), 141-150, 2010
192010
TheoSim: combining symbolic simulation and theorem proving for hardware verification
G Al Sammane, J Schmaltz, D Toma, P Ostier, D Borrione
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
182004
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