Ariane+ NVDLA: seamless third-party IP integration with ESP D Giri, KL Chiu, G Eichler, P Mantovani, N Chandramoorth, LP Carloni Workshop on Computer Architecture Research with RISC-V (CARRV), 2020 | 6 | 2020 |
Accelerator Integration for Open-Source SoC Design D Giri, KL Chiu, G Eichler, P Mantovani, LP Carloni IEEE Micro 41 (4), 8-14, 2021 | 5 | 2021 |
MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces G Eichler, L Piccolboni, D Giri, LP Carloni 2021 IEEE 39th International Conference on Computer Design (ICCD), 101-108, 2021 | 3 | 2021 |
Secondary Reviewers PP Bernardo, A Bhattacharya, P Chakraborty, TY Chen, C Cheng, K Chiu, ... | | |