| A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning X Wu, V Saxena, K Zhu, S Balagopal IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1088-1092, 2015 | 160 | 2015 |
| Homogeneous spiking neuromorphic system for real-world pattern recognition X Wu, V Saxena, K Zhu IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 83 | 2015 |
| Compensation of CMOS op-amps using split-length transistors V Saxena, RJ Baker 2008 51st Midwest Symposium on Circuits and Systems, 109-112, 2008 | 70 | 2008 |
| Indirect feedback compensation of CMOS op-amps V Saxena, RJ Baker 2006 IEEE Workshop on Microelectronics and Electron Devices, 2006. WMED'06 …, 2006 | 57 | 2006 |
| A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing X Wu, V Saxena, K Zhu 2015 International Joint Conference on Neural Networks (IJCNN), 1-6, 2015 | 52 | 2015 |
| Reconfigurable threshold logic gates using memristive devices A Rothenbuhler, T Tran, EHB Smith, V Saxena, KA Campbell Journal of Low Power Electronics and Applications 3 (2), 174-193, 2013 | 47 | 2013 |
| Indirect compensation techniques for three-stage fully-differential op-amps V Saxena, RJ Baker 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 588-591, 2010 | 47 | 2010 |
| Design of Bandpass Delta Sigma Modulators: Avoiding Common Mistakes RJ Baker, V Saxena various universities and companies 30, 2007 | 41 | 2007 |
| Design and Fabrication of a MEMS Capacitive Chemical Sensor System, proceedings of the IEEE V Saxena, TJ Plum, JR Jessing, RJ Baker EDS Workshop on Microelectronics and Electron Devices (WMED), 17-18, 2006 | 40 | 2006 |
| High Speed Digital Input Buffer Circuits, proceedings of the IEEE K Duvvada, V Saxena, RJ Baker EDS Workshop on Microelectronics and Electron Devices (WMED), 11-12, 2006 | 40 | 2006 |
| A compact CMOS memristor emulator circuit and its applications V Saxena 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 37 | 2018 |
| Indirect feedback compensation technique for multi-stage operational amplifiers V Saxena | 37 | 2007 |
| Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design K Zhu, V Saxena, W Kuang 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 36 | 2014 |
| Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models MJ Shawon, V Saxena IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 | 33 | 2020 |
| Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models MJ Shawon, V Saxena IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), 2019 | 33 | 2019 |
| Indirect compensation techniques for three-stage CMOS op-amps V Saxena, RJ Baker 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 9-12, 2009 | 32 | 2009 |
| Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency V Saxena, X Wu, I Srivastava, K Zhu (invited) Journal of Low Power Electronics and Applications (JLPEA) 8 (4), 34, 2018 | 31 | 2018 |
| Design considerations for traveling-wave modulator-based CMOS photonic transmitters K Zhu, V Saxena, X Wu, W Kuang IEEE Transactions on Circuits and Systems II: Express Briefs 62 (4), 412-416, 2015 | 31 | 2015 |
| A deep unsupervised feature learning spiking neural network with binarized classification layers for the EMNIST classification R Vaila, J Chiasson, V Saxena IEEE transactions on emerging topics in computational intelligence 6 (1 …, 2020 | 30 | 2020 |
| A 3D-integrated 56 Gb/s NRZ/PAM4 reconfigurable segmented Mach-Zehnder modulator-based Si-photonics transmitter C Li, K Yu, J Rhim, K Zhu, N Qi, M Fiorentino, T Pinguet, M Peterson, ... 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and …, 2018 | 30 | 2018 |
Kehan ZhuMaxim IntegratedVerified email at maximintegrated.com
