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Igor Murashko, Мурашко И.А.
Igor Murashko, Мурашко И.А.
Professor of Computer Science, Sukhoi State Technical University of Gomel, ГГТУ им. П.О. Сухого
Verified email at gstu.by
Title
Cited by
Cited by
Year
A peak-power estimation for digital circuits design
V Yarmolik, I Murashko
Fifth Int. Conf.«New Information Technologies».-Minsk: BSEU, 34-38, 2002
92002
Transparent Testing of Digital Memories
VN Yarmolik, IA Murashko, A Kummert, AA Ivaniuk
Minsk Bielarus, Bestprint, 2005
82005
The power consumption reducing technique of the pseudo-random test pattern generator and the signature analyzer for the built-in self-test
I Murashko, V Yarmolik, M Puczko
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th …, 2003
62003
Techniki zmniejszania poboru mocy wykorzystywane podczas wbudowanego samotestowania
M Puczko, I Murashko
Pomiary, Automatyka, Kontrola 51 (6), 56-58, 2006
32006
A new test pattern generator design approach for VLSI built-in self-testing
VN Yarmolik, IA Murashko
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 25-35, 1995
31995
PSEUDORANDOM SEQUENCE GENERATOR BASED ON CELLULAR-AUTOMATA
V YARMOLIK, I MURASHKO
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 9-13, 1993
31993
Pseudo random sequence generator construction using cellular automata
VN Yarmolik, IA Murashko
AUTOMATIC CONTROL AND COMPUTER SCIENCES C/C OF AVTOMATIKA I VYCHISLITEL'NAIA …, 1993
3*1993
Zmniejszanie poboru mocy w samotestujących układach cyfrowych
M Puczko, I Murashko, SV Yarmolik
Pomiary Automatyka Kontrola 53 (7), 3-5, 2007
22007
A High-Speed Pseudorandom Test Pattern Generator
IA Murashko, VN Yarmolik
Russian Microelectronics 30 (1), 59-66, 2001
22001
A new approach to the design of a fast M -sequence generator
IA Murashko
Automatic Control and Computer Sciences 41 (2), 88-92, 2007
12007
A switching activity reducing tecnique for the signature analyzer
I Murashko, V Yarmolik
Минск, БГУ, 2003
12003
Switching Activity Minimization for XOR Gate Decomposition
P Barskar, I Murashko
ГГТУ им. ПО Сухого, 2017
2017
Voice User Identification in Access Control Systems
PA Menshakou, IA Murashko, ПА Меньшаков, ИА Мурашко
БГУИР, 2017
2017
Application of cellular automata with an expanded set of rules to generate pseudo-random test sequences
IA Murashko, DE Khrabrov
Problemy Fiziki, Matematiki i Tekhniki (Problems of Physics, Mathematics and …, 2014
2014
Optimal Low Power XOR Gate Decomposition
P Barskar, I Murashko
БГУИР, 2012
2012
Pseudorandom test pattern generators for built-in self-testing: A power reduction method
IA Murashko, VN Yarmolik
Automation and Remote Control 65 (8), 1265-1275, 2004
2004
High-speed generator for built-in self-testing of multi-chip modules
VN Yarmolik, IA Murashko
Automatic Control and Computer Sciences 33 (2), 51-59, 1999
1999
Built-in self-test scanners for very large-scale integration: a new design approach
IA Murashko, AM Shmidman, VN Yarmolik
Avtomatika i Telemekhanika, 157-167, 1998
1998
The Analysis and Design of a Scan Chain for Built-In VLSI Self-Test
VN Yarmolik, IA Murashko, AM Shmidman
RUSSIAN MICROELECTRONICS C/C OF MIKROELEKTRONIKA 26, 299-302, 1997
1997
Design technique of test pattern generator based on decimation of M-sequence property
VN Yarmolik, IA Murashko
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 44-56, 1997
1997
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