| Field-programmable gate arrays SD Brown, RJ Francis, J Rose, ZG Vranesic Springer Science & Business Media, 1992 | 1174 | 1992 |
| Fundamentals of digital logic with Verilog design SD Brown Tata McGraw-Hill Education, 2007 | 926 | 2007 |
| LegUp: high-level synthesis for FPGA-based processor/accelerator systems A Canis, J Choi, M Aldham, V Zhang, A Kammoona, JH Anderson, ... Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011 | 597 | 2011 |
| FPGA and CPLD architectures: A tutorial S Brown, J Rose IEEE design & test of computers 13 (2), 42-57, 1996 | 473 | 1996 |
| A survey and evaluation of FPGA high-level synthesis tools R Nane, VM Sima, C Pilato, J Choi, B Fort, A Canis, YT Chen, H Hsiao, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 367 | 2015 |
| Architecture of FPGAs and CPLDs: A tutorial S Brown, J Rose IEEE Design and Test of Computers 13 (2), 42-57, 1996 | 341 | 1996 |
| LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems A Canis, J Choi, M Aldham, V Zhang, A Kammoona, T Czajkowski, ... ACM Transactions on Embedded Computing Systems (TECS) 13 (2), 1-27, 2013 | 305 | 2013 |
| Flexibility of interconnection structures for field-programmable gate arrays J Rose, S Brown IEEE Journal of Solid-State Circuits 26 (3), 277-282, 1991 | 290 | 1991 |
| A detailed router for field-programmable gate arrays S Brown, J Rose, ZG Vranesic IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 232 | 1992 |
| A detailed routing algorithm for allocating wire segments in field-programmable gate arrays GG Lemieux, SD Brown Proc. ACM/SIGDA Physical Design Workshop, Lake Arrowhead, CA, 215-226, 1993 | 178 | 1993 |
| Hybrid FPGA architecture A Kaviani, S Brown Fourth International ACM Symposium on Field-Programmable Gate Arrays, 3-9, 1996 | 168 | 1996 |
| Post-publication sharing of data and tools PN Schofield, T Bubela, T Weaver, L Portilla, SD Brown, JM Hancock, ... Nature 461 (7261), 171-173, 2009 | 155 | 2009 |
| Heuristics for area minimization in LUT-based FPGA technology mapping V Manohararajah, SD Brown, ZG Vranesic IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 137 | 2006 |
| Computational field programmable architecture A Kaviani, D Vranesic, S Brown Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No …, 1998 | 131 | 1998 |
| Programmable logic device configured to accommodate multiplication BB Pedersen, S Shumarayev, WJ Huang, V Chan, S Brown, T Ngai, ... US Patent 6,323,680, 2001 | 104 | 2001 |
| FPGA technology mapping: a study of optimality A Ling, DP Singh, SD Brown Proceedings. 42nd Design Automation Conference, 2005., 427-432, 2005 | 87 | 2005 |
| FPGA architectural research: a survey S Brown IEEE Design & Test of Computers 13 (4), 9-15, 1996 | 86 | 1996 |
| A multithreaded soft processor for SoPC area reduction B Fort, D Capalija, ZG Vranesic, SD Brown 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2006 | 84 | 2006 |
| Integrated retiming and placement for field programmable gate arrays DP Singh, SD Brown Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002 | 84 | 2002 |
| On two-step routing for FPGAs GGF Lemieux, SD Brown, D Vranesic Proceedings of the 1997 international symposium on Physical design, 60-66, 1997 | 82 | 1997 |
Jongsok ChoiPh.D, University of TorontoVerified email at mail.utoronto.ca
