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Moon Seok Kim
Moon Seok Kim
Verified email at intel.com
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Year
III-V/Ge MOS device technologies for low power integrated systems
S Takagi, M Noguchi, M Kim, SH Kim, CY Chang, M Yokoyama, K Nishi, ...
Solid-State Electronics 125, 82-102, 2016
552016
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors
S George, A Aziz, X Li, MS Kim, S Datta, J Sampson, SK Gupta, ...
IEEE Computer Society Annual Symposium on VLSI, 2016
472016
A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter
MS Kim, H Liu, X Li, S Datta, V Narayanan
Electron Devices, IEEE Transactions on 61 (11), 3661 - 3667, 2014
362014
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells
MS Kim, W Cane-Wissing, X Li, J Sampson, S Datta, SK Gupta, ...
J. Emerg. Technol. Comput. Syst. 12 (4), 23, 2016
342016
III–V and Ge/strained SOI tunneling FET technologies for low power LSIs
S Takagi, M Kim, M Noguchi, SM Ji, K Nishi, M Takenaka
2015 Symposium on VLSI Technology (VLSI Technology), T22-T23, 2015
312015
Modeling steep slope devices: From circuits to architectures
K Swaminathan, MS Kim, N Chandramoorthy, B Sedighi, R Perricone, ...
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014
282014
Steep Slope Devices: Enabling New Architectural Paradigms
K Swaminathan, X Li, H Liu, MS Kim, J Sampson, V Narayanan
Proceedings of the The 51st Annual Design Automation Conference on Design …, 2014
252014
Low Power Nanoelectronics
UH Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok ...
US Patent 20,150,333,534, 2015
23*2015
Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs
MS Kim, X Li, H Liu, J Sampson, S Datta, V Narayanan
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1-11, 2015
172015
Tunneling MOSFET technologies using III-V/Ge materials
S Takagi, DH Ahn, M Noguchi, T Gotow, K Nishi, M Kim, M Takenaka
2016 IEEE International Electron Devices Meeting (IEDM), 19.5. 1-19.5. 4, 2016
162016
Enabling Power-Efficient Designs with III-V Tunnel FETs
MS Kim, H Liu, X Swaminathan, Karthik, Li, S Datta, V Narayanan
Compound Semiconductor Integrated Circuit Symposium (CSICs), 2014 IEEE, 1 - 4, 2014
152014
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective
A Aziz, W Cane-Wissing, MS Kim, S Datta, N Vijaykrishnan, SK Gupta
VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on, 333 - 338, 2015
142015
Emerging steep-slope devices and circuits: Opportunities and challenges
X Li, MS Kim, S George, A Aziz, M Jerry, N Shukla, J Sampson, S Gupta, ...
Beyond-CMOS Technologies for Next Generation Computer Design, 195-230, 2019
112019
All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter
MS Kim, YB Kim, KK Kim
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest …, 2012
112012
IEEE Symp. on VLSI Technol
S Takagi, MS Kim, M Noguchi, SM Ji, K Nishi, M Takenaka
T22, 2015
92015
Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs
MS Kim, W Cane-Wissing, J Sampson, S Datta, V Narayanan, SK Gupta
VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on, 303-308, 2015
62015
0.18 µm CMOS low power ADPLL with a novel local passive interpolation time-to-digital converter based on tri-state inverter
MS Kim
12012
Digital/Mixed-Signal Circuit Designs with Steep Slope III-V Tunnel Transistors
MS Kim
2016
Design and analysis of the quadfferential amplifier
TM Rookmaaker, MS Kim, YB Kim
Microelectronics Journal 43 (10), 697-707, 2012
2012
Design and analysis of a quad-ferential amplifier
TM Rookmaaker, MS Kim, YB Kim
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest …, 2011
2011
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Articles 1–20