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Binh Pham
Binh Pham
Verified email at nvidia.com - Homepage
Title
Cited by
Cited by
Year
Colt: Coalesced large-reach tlbs
B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012
2412012
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
2382020
Increasing TLB reach by exploiting clustering in page translations
B Pham, A Bhattacharjee, Y Eckert, GH Loh
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1792014
Large pages and lightweight memory management in virtualized environments: Can you have it both ways?
B Pham, J Veselý, GH Loh, A Bhattacharjee
Proceedings of the 48th International Symposium on Microarchitecture, 1-12, 2015
1332015
Using tlb speculation to overcome page splintering in virtual machines
B Pham, J Vesely, GH Loh, A Bhattacharjee
Rutgers University, 2015
222015
TLB shootdown mitigation for low-power many-core servers with L1 virtual caches
B Pham, D Hower, A Bhattacharjee, T Cain
IEEE Computer Architecture Letters 17 (1), 17-20, 2017
172017
Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS
DP Keppel, B Pham
US Patent 11,055,232, 2021
112021
Method and apparatus for multi-level memory early page demotion
B Pham, CB Wilkerson, AR Alameldeen, ZA Chishti, Z Wang
US Patent 10,860,244, 2020
112020
The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
112020
Method and system for performing data movement operations with read snapshot and in place write update
A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ...
US Patent 10,606,755, 2020
92020
System, method, and apparatus for snapshot prefetching to improve performance of snapshot operations
R Wang, LC Stewart, B Pham, A Herdrich, V Krishnan, A Vasudevan, ...
US Patent App. 16/147,346, 2020
82020
Branch prediction based on coherence operations in processors
C Wilkerson, B Pham, P Lu, JW Stark IV
US Patent 10,521,236, 2019
42019
Apparatuses, methods, and systems to accelerate store processing
B Pham, C Dan
US Patent 10,754,782, 2020
22020
Method and system for performing data movement operations with read snapshot and in place write update
A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ...
US Patent 11,327,894, 2022
12022
Programmable address range engine for larger region sizes
E Farah, M Diamond, D Keppel, SS Sury, B Pham, S Vissapragada
US Patent App. 16/786,815, 2020
12020
Architectural support for efficient virtual memory on big-memory systems
BQ Pham
Rutgers The State University of New Jersey, School of Graduate Studies, 2016
12016
Branch prediction based on coherence operations in processors
C Wilkerson, B Pham, P Lu, JW Stark IV
US Patent 11,886,884, 2024
2024
Method and system for performing data movement operations with read snapshot and in place write update
A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ...
US Patent 11,816,036, 2023
2023
Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power
BQ Pham, R Wang
US Patent 10,496,551, 2019
2019
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Articles 1–19