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Pavel Benáček
Pavel Benáček
Researcher at CESNET
Bestätigte E-Mail-Adresse bei cesnet.cz
Titel
Zitiert von
Zitiert von
Jahr
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
P Benáček, V Puš, K Hana
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016
652016
P4-To-VHDL: Automatic generation of high-speed input and output network blocks
P Benáček, V Puš, H Kubátová, T Čejka
Microprocessors and Microsystems 56, 22-33, 2018
322018
Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput
J Cabal, P Benáček, L Kekely, M Kekely, V Puš, J Kořenek
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
312018
Accelerated DDoS attacks mitigation using programmable data plane
M Kuka, K Vojanec, J Kučera, P Benáček
2019 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2019
232019
Generation of High-Speed Network Device from High-Level Description
P Benáček
Faculty of Information Technology Department of Digital Design Generation of …, 2016
112016
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring
L Kekely, V Puš, P Benáček, J Kořenek
2014 24th International Conference on Field Programmable Logic and …, 2014
112014
Line rate programmable packet processing in 100gb networks
P Benáček, V Puš, J Kořenek, M Kekely
2017 27th International Conference on Field Programmable Logic and …, 2017
102017
Change-point detection method on 100 Gb/s ethernet interface
P Benáček, RB Blažek, T Čejka, H Kubátová
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking …, 2014
52014
Scalable P4 deparser for speeds over 100 gbps
J Cabal, P Benácek, J Foltova, J Holub
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
42019
Verification of generated rtl from p4 source code
R Iša, P Benáček, V Puš
2018 IEEE 26th International Conference on Network Protocols (ICNP), 444-445, 2018
32018
FPGA Accelerated Change-Point Detection Method for 100Gb/s Networks
T Cejka, L Kekely, P Benácek, RB Blazek, H Kubátová
9th Doctoral Workshop on Mathematical and Engineering Methods in Computer …, 2014
22014
P4-to-VHDL: How we built the fastest p4 FPGA device in the world
P Benáček
6th Prague Embedded Systems Workshop, 43, 2018
12018
Automatic Generation of 100 Gbps Packet Parsers from P4
P Benácek, V Puš, H Kubátová
12017
Application specific processor with high level synthesized instructions
V Puš, P Benáček
Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014
12014
Ethernetový tester pro vysokorychlostní sítě
P Benáček
České vysoké učení technické v Praze. Vypočetní a informační centrum., 2012
12012
Behavioural Based Forwarding
M Bonola, V Bruschi, D Sanvito, S Pontarelli, G Bianchi, C Cascone, ...
2016
Behavioural Based Forwarding
F Huici, FS NEC, V Puš, M Špinler, P Benáček, G Procissi, N Bonelli, ...
2016
Deliverable title Revision of the BEBA data plane extensions Version 2.0 Due date of deliverable (month)
C Cascone, G Procissi, N Bonelli, P Benáček, M Vaško
2015
Architecture of Effective High-Speed Network Stream Merger
P Benácek, H Kubátová, V Pu
2014 17th Euromicro Conference on Digital System Design, 459-464, 2014
2014
Case Study: Usage of High Level Synthesis in HPC Networking
P Benácek, L Richter, M Kekely, V Puš
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