Matthias Jung
Matthias Jung
Expert Engineer at Fraunhofer IESE
Bestätigte E-Mail-Adresse bei iese.fraunhofer.de - Startseite
Titel
Zitiert von
Zitiert von
Jahr
DRAMPower: Open-source DRAM Power & Energy Estimation Tool
K Chandrasekar, C Weis, Y Li, S Goossens, M Jung, O Naji, B Akesson, ...
http://www.drampower.info, 2014
1372014
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework
M Jung, C Weis, N Wehn
IPSJ Transactions on System LSI Design Methodology 8, 63-74, 2015
522015
Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM
M Jung, DM Mathew, C Weis, N Wehn
Design Automation Conference (DAC), 2016
452016
TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems: a Virtual Platform for Memory Controller Design Space Exploration
M Jung, C Weis, N Wehn, K Chandrasekar
Workshop on Rapid Simulation and Performance Evaluation 2013 (RAPIDO) HiPEAC …, 2013
442013
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs
M Jung, É Zulian, DM Mathew, M Herrmann, C Brugger, C Weis, N Wehn
International Symposium On Memory Systems (MEMSYS '15), 85-91, 2015
412015
System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C Menard, M Jung, J Castrillon, N Wehn
IEEE International Conference on Embedded Computer Systems Architectures …, 2017
362017
Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-Wise Refresh
M Sadri, M Jung, C Weis, N Wehn, L Benini
Proceedings of the conference on Design, Automation & Test in Europe, 281, 2014
362014
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
332020
Reverse Engineering of DRAMs: Row Hammer with Crosshair
M Jung, C Rheinländer, C Weis, N Wehn
International Symposium on Memory Systems (MEMSYS 2016), 2016
322016
Efficient Reliability Management in SoCs - An Approximate DRAM Perspective
M Jung, DM Mathew, C Weis, N Wehn
21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016
322016
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
C Weis, M Jung, P Ehses, C Santos, S Pascal Vivet, Goossens, ...
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
322015
A Platform to Analyze DDR3 DRAM's Power and Retention Time
M Jung, DM Mathew, CC Rheinlander, C Weis, N Wehn
IEEE Design & Test, 2017
292017
Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
R Jagtap, S Diestelhorst, A Hansson, M Jung, N Wehn
IEEE International Conference on Embedded Computer Systems Architectures …, 2016
262016
A high-level DRAM timing, power and area exploration tool
O Naji, C Weis, M Jung, N Wehn, A Hansson
2015 International Conference on Embedded Computer Systems: Architectures …, 2015
262015
ConGen: An Application Specific DRAM Memory Controller Generator
M Jung, I Heinrich, M Natale, DM Mathew, C Weis, S Krumke, N Wehn
International Symposium on Memory Systems (MEMSYS 2016), 2016
222016
Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms
M Jung, C Weis, P Bertram, G Braun, N Wehn
Synopsys Usergroup Conference (SNUG), 2013
212013
A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M Jung, DM Mathew, ÉF Zulian, C Weis, N Wehn
International Workshop on Power And Timing Modeling, Optimization and …, 2016
172016
Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
M Jung, M Sadri, C Weis, N Wehn, L Benini
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2014
162014
A Bank-Wise DRAM Power Model for System Simulations
D Mathew, É Zulian, S Kannoth, M Jung, C Weis, N Wehn
Workshop on: Rapid Simulation Simulation and Performance Evaluation: Methods …, 2017
142017
DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool
C Weis, A Mutaal, O Naji, M Jung, A Hansson, N Wehn
International Journal of Parallel Programming (IJPP), 2016
132016
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