Jan Reineke
Jan Reineke
Professor of Computer Science, Saarland University, Saarland Informatics Campus
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Zitiert von
Zitiert von
CacheAudit: A Tool for the Static Analysis of Cache Side Channels
G Doychev, B Köpf, L Mauborgne, J Reineke
ACM Transactions on Information and System Security (TISSEC), 2015
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
R Wilhelm, D Grund, J Reineke, M Schlickling, M Pister, C Ferdinand
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
A definition and classification of timing anomalies
J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ...
6th International Workshop on Worst-Case Execution Time Analysis (WCET), 2006
Timing predictability of cache replacement policies
J Reineke, D Grund, C Berg, R Wilhelm
Real-Time Systems 37, 99-122, 2007
PRET DRAM controller: Bank privatization for predictability and temporal isolation
J Reineke, I Liu, HD Patel, S Kim, EA Lee
IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and …, 2011
SPECTECTOR: Principled Detection of Speculative Information Flows
M Guarnieri, B Köpf, JF Morales, J Reineke, A Sánchez
IEEE Symposium on Security and Privacy (S&P), 2020
Building timing predictable embedded systems
P Axer, R Ernst, H Falk, A Girault, D Grund, N Guan, B Jonsson, ...
ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-37, 2014
Predictability considerations in the design of multi-core embedded systems
C Cullmann, C Ferdinand, G Gebhard, D Grund, C Maiza, J Reineke, ...
Embedded Real Time Software and Systems (ERTSS), 36-42, 2010
A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance
I Liu, J Reineke, D Broman, M Zimmer, EA Lee
30th International IEEE Conference on Computer Design (ICCD), 2012
Towards Compositionality in Execution Time Analysis–Definition and Challenges
S Hahn, J Reineke, R Wilhelm
6th International Workshop on Compositional Theory and Technology for Real …, 2013
1192013 Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A Abel, J Reineke
ASPLOS, 673-686, 2019
Hardware-Software Contracts for Secure Speculation
M Guarnieri, B Köpf, J Reineke, P Vila
IEEE Symposium on Security and Privacy (S&P), 2021
A PRET architecture supporting concurrent programs with composable timing properties
I Liu, J Reineke, EA Lee
44th Asilomar Conference on Signals, Systems and Computers, 2111-2115, 2010
Temporal isolation on multiprocessing architectures
D Bui, E Lee, I Liu, H Patel, J Reineke
48th Annual ACM/EDAC/IEEE Design Automation Conference (DAC), 274-279, 2011
A survey on static cache analysis for real-time systems
M Lv, N Guan, J Reineke, R Wilhelm, W Yi
Leibniz Transactions on Embedded Systems (LITES) 3 (1), 05-1-05: 48, 2016
Resilience Analysis: Tightening the CRPD bound for set-associative caches
S Altmeyer, C Maiza, J Reineke
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for …, 2010
A generic and compositional framework for multicore response time analysis
S Altmeyer, RI Davis, L Indrusiak, C Maiza, V Nelis, J Reineke
23rd International Conference on Real-Time Networks and Systems (RTNS), 129-138, 2015
Impact of Resource Sharing on Performance and Performance Prediction: A Survey
A Abel, F Benz, J Doerfert, B Dörr, S Hahn, F Haupenthal, M Jacobs, ...
24th International Conference on Concurrency Theory (CONCUR), 2013
Caches in WCET analysis
J Reineke
Universität des Saarlandes, Saarbrücken, PhD Thesis, 2008
Embedded Systems: Many Cores–Many Problems
R Wilhelm, J Reineke
7th IEEE International Symposium on Industrial Embedded Systems (SIES), 2012
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