Jan Reineke - Google Scholar Citations

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Citations	2799	1652
h-index	29	21
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Co-authors

Daniel GrundSaarland UniversityVerified email at cs.uni-saarland.de
Reinhard WilhelmComputer Science, Saarland University, Saarland Informatics Campus (SIC)Verified email at cs.uni-saarland.de
claire maizaGrenobleINP / VerimagVerified email at univ-grenoble-alpes.fr
Sebastian AltmeyerUniversity of AugsburgVerified email at uva.nl
Sebastian HahnSaarland UniversityVerified email at cs.uni-saarland.de
Edward A. LEEProfessor of Electrical Engineering and Computer Sciences, University of California at BerkeleyVerified email at berkeley.edu
Andreas AbelSaarland University, GermanyVerified email at cs.uni-saarland.de
Boris KöpfMicrosoft ResearchVerified email at microsoft.com
Wang YiProfessor of Embedded Systems, Uppsala UniversityVerified email at it.uu.se
Nan GuanThe Hong Kong Polytechnic UniversityVerified email at comp.polyu.edu.hk
Hiren PatelUniversity of WaterlooVerified email at uwaterloo.ca
Björn WachterUniversity of OxfordVerified email at cs.ox.ac.uk
Rob DavisReader, Real-Time Systems Research Group (RTSRG), University of York, UK.Verified email at york.ac.uk
Christine RochangeVerified email at irit.fr
Christoph CullmannAbsInt Angewandte Informatik GmbHVerified email at absint.com
Michael ZimmerVerified email at eecs.berkeley.edu
Heiko FalkInstitute of Embedded Systems, Hamburg University of Technology (TUHH)Verified email at tuhh.de
Bengt JonssonProfessor of Computer Systems, Uppsala UniversityVerified email at it.uu.se
Reinhard von HanxledenDepartment of Computer Science, Kiel UniversityVerified email at informatik.uni-kiel.de
Bernd BeckerProfessor of Computer Science, University of FreiburgVerified email at informatik.uni-freiburg.de

Jan Reineke

Professor of Computer Science, Saarland University, Saarland Informatics Campus

Verified email at cs.uni-saarland.de - Homepage

Static Analysis WCET Analysis Real-time Systems Abstract Interpretation


Title	Cited by	Year
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems R Wilhelm, D Grund, J Reineke, M Schlickling, M Pister, C Ferdinand IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009	266	2009
A definition and classification of timing anomalies J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ... 6th International Workshop on Worst-Case Execution Time Analysis (WCET), 2006	217	2006
Timing predictability of cache replacement policies J Reineke, D Grund, C Berg, R Wilhelm Real-Time Systems 37 (2), 99-122, 2007	207	2007
PRET DRAM controller: Bank privatization for predictability and temporal isolation J Reineke, I Liu, HD Patel, S Kim, EA Lee IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and …, 2011	195	2011
CacheAudit: A Tool for the Static Analysis of Cache Side Channels G Doychev, B Köpf, L Mauborgne, J Reineke ACM Transactions on Information and System Security (TISSEC), 2015	173	2015
Predictability considerations in the design of multi-core embedded systems C Cullmann, C Ferdinand, G Gebhard, D Grund, C Maiza, J Reineke, ... Embedded Real Time Software and Systems (ERTSS), 36-42, 2010	114	2010
Building timing predictable embedded systems P Axer, R Ernst, H Falk, A Girault, D Grund, N Guan, B Jonsson, ... ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-37, 2014	101	2014
A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance I Liu, J Reineke, D Broman, M Zimmer, EA Lee 30th International IEEE Conference on Computer Design (ICCD), 2012	97	2012
Towards Compositionality in Execution Time Analysis–Definition and Challenges S Hahn, J Reineke, R Wilhelm 6th International Workshop on Compositional Theory and Technology for Real …, 2013	73	2013
A PRET architecture supporting concurrent programs with composable timing properties I Liu, J Reineke, EA Lee 44th Asilomar Conference on Signals, Systems and Computers, 2111-2115, 2010	70	2010
Resilience Analysis: Tightening the CRPD bound for set-associative caches S Altmeyer, C Maiza, J Reineke ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for …, 2010	69	2010
Caches in WCET analysis J Reineke Universität des Saarlandes, Saarbrücken, PhD Thesis, 2008	66*	2008
Temporal isolation on multiprocessing architectures D Bui, E Lee, I Liu, H Patel, J Reineke 48th Annual ACM/EDAC/IEEE Design Automation Conference (DAC), 274-279, 2011	64	2011
Impact of Resource Sharing on Performance and Performance Prediction: A Survey A Abel, F Benz, J Doerfert, B Dörr, S Hahn, F Haupenthal, M Jacobs, ... 24th International Conference on Concurrency Theory (CONCUR), 2013	56	2013
Relative competitive analysis of cache replacement policies J Reineke, D Grund ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for …, 2008	53	2008
A generic and compositional framework for multicore response time analysis S Altmeyer, RI Davis, L Indrusiak, C Maiza, V Nelis, J Reineke 23rd International Conference on Real-Time Networks and Systems (RTNS), 129-138, 2015	50	2015
Precise and efficient FIFO-replacement analysis based on static phase detection D Grund, J Reineke 22nd Euromicro Conference on Real-Time Systems (ECRTS), 155-164, 2010	50	2010
Randomized caches considered harmful in hard real-time systems J Reineke Leibniz Transactions on Embedded Systems (LITES) 1 (1), 03-1-03: 13, 2014	45	2014
CAMA: A predictable cache-aware memory allocator J Herter, P Backes, F Haupenthal, J Reineke 23rd Euromicro Conference on Real-Time Systems (ECRTS), 23-32, 2011	44	2011
Abstract interpretation of FIFO replacement D Grund, J Reineke International Static Analysis Symposium (SAS), 120-136, 2009	41	2009

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