| Reliable on-chip systems in the nano-era: Lessons learnt and future trends J Henkel, L Bauer, N Dutt, P Gupta, S Nassif, M Shafique, M Tahoori, ... Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013 | 246 | 2013 |
| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 196 | 2020 |
| DRAMPower: Open-source DRAM power & energy estimation tool K Chandrasekar, C Weis, Y Li, B Akesson, N Wehn, K Goossens URL: http://www. drampower. info 22, 2012 | 184 | 2012 |
| Turbo-decoding without SNR estimation A Worm, P Hoeher, N Wehn IEEE Communications Letters 4 (6), 193-195, 2000 | 180 | 2000 |
| A synthesizable IP core for DVB-S2 LDPC code decoding F Kienle, T Brack, N Wehn Design, Automation and Test in Europe, 100-105, 2005 | 151 | 2005 |
| A synthesizable IP core for WIMAX 802.16 e LDPC code decoding T Brack, M Alles, F Kienle, N Wehn 2006 IEEE 17th international symposium on personal, indoor and mobile radio …, 2006 | 141 | 2006 |
| A 477mW NoC-based digital baseband for MIMO 4G SDR F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 278-279, 2010 | 125 | 2010 |
| Low complexity LDPC code decoders for next generation standards T Brack, M Alles, T Lehnigk-Emden, F Kienle, N Wehn, NE L'Insalata, ... 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 120 | 2007 |
| Database of channel codes and ML simulation results M Helmling, S Scholl, F Gensheimer, T Dietz, K Kraft, S Ruzika, N Wehn www. uni-kl. de/channel-codes, 0733-8716, 2019 | 116 | 2019 |
| Design and architectures for dependable embedded systems J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ... Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011 | 116 | 2011 |
| Automating RT-level operand isolation to minimize power consumption in datapaths M Münch, B Wurth, R Mehra, J Sproch, N Wehn Proceedings of the conference on Design, automation and test in Europe, 624-633, 2000 | 113 | 2000 |
| Network-on-chip-centric approach to interleaving in high throughput channel decoders C Neeb, MJ Thul, N Wehn 2005 IEEE International Symposium on Circuits and Systems, 1766-1769, 2005 | 107 | 2005 |
| A 150Mbit/s 3GPP LTE turbo code decoder M May, T Ilnseher, N Wehn, W Raab 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 105 | 2010 |
| Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ M Sadri, C Weis, N Wehn, L Benini Proceedings of the 10th FPGAworld Conference, 1-8, 2013 | 102 | 2013 |
| Exploiting expendable process-margins in DRAMs for run-time performance optimization K Chandrasekar, S Goossens, C Weis, M Koedam, B Akesson, N Wehn, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 97 | 2014 |
| FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding M Alles, T Vogt, N Wehn 2008 5th International symposium on turbo codes and related topics, 84-89, 2008 | 95 | 2008 |
| Low complexity stopping criterion for LDPC code decoders F Kienle, N Wehn 2005 IEEE 61st Vehicular Technology Conference 1, 606-609, 2005 | 95 | 2005 |
| Monitoring household activities and user location with a cheap, unobtrusive thermal sensor array P Hevesi, S Wille, G Pirkl, N Wehn, P Lukowicz Proceedings of the 2014 ACM international joint conference on pervasive and …, 2014 | 91 | 2014 |
| Embedded DRAM development: Technology, physical design, and application issues D Keitel-Schulz, N Wehn IEEE Design & Test of Computers 18 (3), 7-15, 2001 | 87 | 2001 |
| A scalable system architecture for high-throughput turbo-decoders MJ Thul, F Gilbert, T Vogt, G Kreiselmaier, N Wehn Journal of VLSI signal processing systems for signal, image and video …, 2005 | 86 | 2005 |
