Sybille Hellebrand
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Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
S Hellebrand, J Rajski, S Tarnick, S Venkataraman, B Courtois
IEEE Transactions on Computers 44 (2), 223-233, 1995
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
S Hellebrand, S Tarnick, B Courtois, J Rajski
ITC, 120-129, 1992
Pattern generation for a deterministic BIST scheme
S Hellebrand, B Reeb, S Tarnick, HJ Wunderlich
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
A mixed mode BIST scheme based on reseeding of folding counters
S Hellebrand, HG Liang, HJ Wunderlich
Journal of Electronic Testing 17 (3), 341-349, 2001
Two-dimensional test data compression for scan-based deterministic BIST
HG Liang, S Hellebrand, HJ Wunderlich
Journal of Electronic Testing 18 (2), 159-170, 2002
An efficient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers
S Venkataraman, J Rajski, S Hellebrand, S Tarnick
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993
An integrated built-in test and repair approach for memories with 2D redundancy
P Ohler, S Hellebrand, HJ Wunderlich
12th IEEE European Test Symposium (ETS'07), 91-96, 2007
Data compression for multiple scan chains using dictionaries with corrections
A Wurtenberger, CS Tautermann, S Hellebrand
2004 International Conferce on Test, 926-935, 2004
Mixed-mode BIST using embedded processors
S Hellebrand, HJ Wunderlich, A Hertwig
On-Line Testing for VLSI, 127-138, 1998
A fault tolerant mechanism for handling permanent and transient failures in a network on chip
M Ali, M Welzl, S Hessler
Fourth International Conference on Information Technology (ITNG'07), 1027-1032, 2007
The pseudoexhaustive test of sequential circuits
HJ Wunderlich, S Hellebrand
IEEE transactions on computer-aided design of integrated circuits and …, 1992
A high performance SEU tolerant latch
Z Huang, H Liang, S Hellebrand
Journal of Electronic Testing 31 (4), 349-359, 2015
A hybrid coding strategy for optimized test data compression
A Würtenberger, CS Tautermann, S Hellebrand
ITC 3, 451-459, 2003
Symmetric transparent BIST for RAMs
VN Yarmolik, S Hellebrand, HJ Wunderlich
Design, Automation and Test in Europe Conference and Exhibition 1999 …, 1999
A dynamic routing mechanism for network on chip
M Ali, M Welzl, S Hellebrand
2005 NORCHIP, 70-73, 2005
STARBIST: Scan autocorrelated random pattern generation
KH Tsai, S Hellebrand, J Rajski, M Marek-Sadowska
Proceedings of the 34th annual Design Automation Conference, 472-477, 1997
Efficient online and offline testing of embedded DRAMs
S Hellebrand, HJ Wunderlich, AA Ivaniuk, YV Klimets, VN Yarmolik
IEEE Transactions on Computers 51 (7), 801-809, 2002
Alternating run-length coding--a technique for improved test data compression
S Hellebrand, A Würtenberger
Considerations for fault-tolerant network on chips
M Ali, M Welzl, M Zwicknagl, S Hellebrand
2005 International Conference on Microelectronics, 5 pp., 2005
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip
M Ali, M Welzl, S Hessler, S Hellebrand
International Journal of High Performance Systems Architecture 1 (2), 113-123, 2007
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