Deepak M Mathew
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Zitiert von
Jahr
Approximate computing with partially unreliable dynamic random access memory-approximate DRAM
M Jung, DM Mathew, C Weis, N Wehn
Proceedings of the 53rd Annual Design Automation Conference, 1-4, 2016
352016
Omitting refresh: A case study for commodity and wide i/o drams
M Jung, É Zulian, DM Mathew, M Herrmann, C Brugger, C Weis, N Wehn
Proceedings of the 2015 International Symposium on Memory Systems, 85-91, 2015
302015
Efficient reliability management in SoCs-an approximate DRAM perspective
M Jung, DM Mathew, C Weis, N Wehn
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 390-394, 2016
272016
A platform to analyze DDR3 DRAM’s power and retention time
M Jung, DM Mathew, CC Rheinländer, C Weis, N Wehn
IEEE Design & Test 34 (4), 52-59, 2017
222017
Congen: An application specific dram memory controller generator
M Jung, DM Mathew, C Weis, N Wehn, I Heinrich, MV Natale, SO Krumke
Proceedings of the Second International Symposium on Memory Systems, 257-267, 2016
152016
A new bank sensitive DRAMPower model for efficient design space exploration
M Jung, DM Mathew, ÉF Zulian, C Weis, N Wehn
2016 26th International Workshop on Power and Timing Modeling, Optimization …, 2016
152016
Bedarfsorientierte Gestaltung hochschulischer Bildungsangebote für eine erweiterte gemeindenahe Pflegepraxis
AK Helbig, T Steuerwald, D Arnold
132017
A bank-wise dram power model for system simulations
DM Mathew, ÉF Zulian, S Kannoth, M Jung, C Weis, N Wehn
Proceedings of the 9th Workshop on Rapid Simulation and Performance …, 2017
112017
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
DM Mathew, M Schultheis, CC Rheinländer, C Sudarshan, C Weis, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 293-296, 2018
92018
Improving the error behavior of DRAM by exploiting its Z-channel property
K Kraft, C Sudarshan, DM Mathew, C Weis, N Wehn, M Jung
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
82018
The role of memories in transprecision computing
C Weis, M Jung, ÉF Zulian, C Sudarshan, DM Mathew, N Wehn
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
42018
Using run-time reverse-engineering to optimize DRAM refresh
DM Mathew, ÉF Zulian, M Jung, K Kraft, C Weis, B Jacob, N Wehn
Proceedings of the International Symposium on Memory Systems, 115-124, 2017
42017
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C Sudarshan, J Lappas, C Weis, DM Mathew, M Jung, N Wehn
International Conference on Embedded Computer Systems, 429-441, 2019
32019
Efficient coding scheme for DDR4 memory subsystems
K Kraft, DM Mathew, C Sudarshan, M Jung, C Weis, N Wehn, F Longnos
Proceedings of the International Symposium on Memory Systems, 148-157, 2018
32018
RRAMSpec: A design space exploration framework for high density resistive RAM
DM Mathew, AL Chinazzo, C Weis, M Jung, B Giraud, P Vivet, A Levisse, ...
International Conference on Embedded Computer Systems, 34-47, 2019
22019
Using runtime reverse engineering to optimize DRAM refresh
DM Mathew, M Jung, C Weis, N Wehn
US Patent 10,622,054, 2020
2020
Omitting Refresh
M Jung, É Zulian, DM Mathew, M Herrmann, C Brugger, C Weis, N Wehn
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