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Seokhyeong Kang
Seokhyeong Kang
Bestätigte E-Mail-Adresse bei postech.ac.kr - Startseite
Titel
Zitiert von
Zitiert von
Jahr
Accuracy-configurable adder for approximate arithmetic designs
AB Kahng, S Kang
Proceedings of the 49th Annual Design Automation Conference, 820-825, 2012
5122012
Slack redistribution for graceful degradation under voltage overscaling
AB Kahng, S Kang, R Kumar, J Sartori
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 825-831, 2010
2122010
Designing a processor from the ground up to allow voltage/reliability tradeoffs
AB Kahng, S Kang, R Kumar, J Sartori
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
1372010
Statistical analysis and modeling for error composition in approximate computation circuits
WTJ Chan, AB Kahng, S Kang, R Kumar, J Sartori
2013 IEEE 31st International Conference on Computer Design (ICCD), 47-53, 2013
722013
Sensitivity-guided metaheuristics for accurate discrete gate sizing
J Hu, AB Kahng, SH Kang, MC Kim, IL Markov
Proceedings of the International Conference on Computer-Aided Design, 233-239, 2012
692012
Recovery-driven design: A power minimization methodology for error-tolerant processor modules
AB Kahng, S Kang, R Kumar, J Sartori
Design Automation Conference, 825-830, 2010
652010
Enhancing the efficiency of energy-constrained DVFS designs
AB Kahng, S Kang, R Kumar, J Sartori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (10 …, 2012
472012
Ternary full adder using multi-threshold voltage graphene barristors
S Heo, S Kim, K Kim, H Lee, SY Kim, YJ Kim, SM Kim, HI Lee, S Lee, ...
IEEE Electron Device Letters 39 (12), 1948-1951, 2018
392018
High-performance gate sizing with a signoff timer
AB Kahng, S Kang, H Lee, IL Markov, P Thapar
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 450-457, 2013
382013
Learning-based approximation of interconnect delay and slew in signoff timing tools
AB Kahng, S Kang, H Lee, S Nath, J Wadhwani
2013 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2013
352013
MAPG: Memory access power gating
K Jeong, AB Kahng, S Kang, TS Rosing, R Strong
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
352012
An optimal gate design for the synthesis of ternary logic circuits
S Kim, T Lim, S Kang
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 476-481, 2018
332018
A logic synthesis methodology for low-power ternary logic circuits
S Kim, SY Lee, S Park, KR Kim, S Kang
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3138-3151, 2020
322020
A novel ternary multiplier based on ternary CMOS compact model
Y Kang, J Kim, S Kim, S Shin, ES Jang, JW Jeong, KR Kim, S Kang
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 25-30, 2017
292017
Many-core token-based adaptive power gating
AB Kahng, S Kang, TS Rosing, R Strong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
222013
Active-mode leakage reduction with data-retained power gating
AB Kahng, S Kang, B Park
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
222013
TAP: token-based adaptive power gating
AB Kahng, S Kang, T Rosing, R Strong
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
202012
Smart non-default routing for clock power reduction
AB Kahng, S Kang, H Lee
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-7, 2013
152013
Construction of realistic gate sizing benchmarks with known optimal solutions
AB Kahng, S Kang
Proceedings of the 2012 ACM international symposium on International …, 2012
142012
A new methodology for reduced cost of resilience
AB Kahng, S Kang, J Li
Proceedings of the 24th edition of the great lakes symposium on VLSI, 157-162, 2014
112014
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