Süleyman Savas
Süleyman Savas
Zurich Research Center, Huawei Technologies Switzerland
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Cited by
Cited by
Efficient single-precision floating-point division using harmonized parabolic synthesis
S Savas, E Hertz, T Nordström, Z Ul-Abdin
2017 IEEE computer society annual symposium on VLSI (ISVLSI), 110-115, 2017
Designing domain-specific heterogeneous architectures from dataflow programs
S Savas, Z Ul-Abdin, T Nordström
Computers 7 (2), 27, 2018
A communication library for mapping dataflow applications on manycore architectures
M Yang, S Savas, Z Ul-Abdin, T Nordström
6th Swedish Multicore Computing Workshop, MCC-2013, November 25-26 2013 …, 2013
A framework to generate domain-specific manycore architectures from dataflow programs
S Savas, Z Ul-Abdin, T Nordström
Microprocessors and microsystems 72, 102908, 2020
An evaluation of code generation of dataflow languages on manycore architectures
S Savas, E Gebrewahid, Z Ul-Abdin, T Nordström, M Yang
2014 IEEE 20th International Conference on Embedded and Real-Time Computing …, 2014
Dataflow implementation of qr decomposition on a manycore
S Savas, S Raase, E Gebrewahid, Z Ul-Abdin, T Nordström
Proceedings of the Third ACM International Workshop on Many-core Embedded …, 2016
Towards Architectural Design Space Exploration for Heterogeneous Manycores
B Xypolitidis, R Shabani, SV Khandeparkar, Z Ul-Abdin, S Savas, ...
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
Linear algebra for array signal processing on a massively parallel dataflow architecture
S Savaş
Högskolan i Halmstad/Sektionen för Informationsvetenskap, Data-och …, 2009
Using harmonized parabolic synthesis to implement a single-precision floating-point square root unit
S Savas, Y Atwa, T Nordström, Z Ul-Abdin
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 621-626, 2019
A configurable two dimensional mesh Network-on-Chip implementation in chisel
S Savas, Z Ul-Abdin, T Nordström
Utilizing Heterogeneity in Manycore Architectures for Streaming Applications
S Savas
Halmstad University Press, 2017
Implementation and evaluation of mpeg-4 simple profile decoder on a massively parallel processor array
S Savas
Hardware/Software Co-Design of Heterogeneous Manycore Architectures
S Savas
Halmstad University Press, 2019
Generating hardware and software for RISC-V cores generated with Rocket Chip generator
S Savas, E Bezati, JW Janneck
2021 IEEE 34th International System-on-Chip Conference (SOCC), 89-94, 2021
Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks
S Savas, Z Ul-Abdin, T Nordström
Designing Domain Specific Heterogeneous Manycores from Dataflow Programs
S Savas
Supporting efficient channel-based communication in a mesh network-on-chip
S Raase, S Savas, Z Ul-Abdin, T Nordström
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