| Deadline, energy and buffer-aware task mapping optimization in noc-based socs using genetic algorithms JV Bruch, EA Da Silva, CA Zeferino, LS Indrusiak 2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 86-93, 2017 | 14 | 2017 |
| BrownPepper: A SystemC-based simulator for performance evaluation of Networks-on-Chip JV Bruch, MR Pizzoni, CA Zeferino 2009 17th IFIP International Conference on Very Large Scale Integration …, 2009 | 12 | 2009 |
| Avaliação de desempenho de rede-em-chip modelada em systemc CA Zeferino, JV Bruch, TF Pereira, ME Kreutz, AA Susin Proceedings of the 27rd Congress of Brazilian Computer Society-WPerformance …, 2007 | 8 | 2007 |
| Evaluation of Architectural Alternatives to Reduce Power Consumption in a Network-on-Chip JV BRUCH, CA ZEFERINO 2nd Workshop on Circuits and Systems Design (WCAS 2012), 2012 | 2 | 2012 |
| A SystemC-based environment for performance evaluation of Networks-on-Chip JV BRUCH, CA ZEFERINO, RL CANCIAN South Symposium on Microelectronics, 45-48, 2008 | 2 | 2008 |
Cesar Albenes ZeferinoProfessor of Computer Science, University of Vale do ItajaíVerified email at univali.br
