| DeNovo: Rethinking the memory hierarchy for disciplined parallelism B Choi, R Komuravelli, H Sung, R Smolinski, N Honarmand, SV Adve, ... 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 203 | 2011 |
| A simple method for parameterized verification of cache coherence protocols CT Chou, PK Mannava, S Park International Conference on Formal Methods in Computer-Aided Design, 382-398, 2004 | 134 | 2004 |
| Formal verification of a partial-order reduction technique for model checking CT Chou, D Peled Journal of Automated Reasoning 23 (3), 265-298, 1999 | 108* | 1999 |
| The mathematical foundation of symbolic trajectory evaluation CT Chou International Conference on Computer Aided Verification, 196-207, 1999 | 69 | 1999 |
| Understanding and verifying distributed algorithms using stratified decomposition CT Chou, E Gafni Proceedings of the seventh annual ACM Symposium on Principles of distributed …, 1988 | 60 | 1988 |
| Synchronizing asynchronous bounded delay networks CT Chou, I Cidon, IS Gopal, S Zaks IEEE Transactions on communications 38 (2), 144-147, 1990 | 55 | 1990 |
| Reducing verification complexity of a multicore coherence protocol using assume/guarantee X Chen, Y Yang, G Gopalakrishnan, CT Chou 2006 Formal Methods in Computer Aided Design, 81-88, 2006 | 46 | 2006 |
| Mechanical verification of distributed algorithms in higher-order logic CT Chou The Computer Journal 38 (2), 152-161, 1995 | 46 | 1995 |
| Interconnect architectural state coverage measurement methodology P Mannava, S Park, A Dingankar, CT Chou, N Mittal, RV Mahalikudi, ... US Patent App. 11/965,158, 2009 | 33 | 2009 |
| A formal theory of undirected graphs in higher-order logc CT Chou HOL Users' Group Workshop, 144-157, 1994 | 33 | 1994 |
| Revisiting the complexity of hardware cache coherence and some implications R Komuravelli, SV Adve, CT Chou ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-22, 2014 | 30 | 2014 |
| Link level retry scheme CT Chou, S Chittor, A Khan, A Kumar, PK Mannava, RS Ram, S Sen, ... US Patent 7,016,304, 2006 | 30* | 2006 |
| A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® Itanium™ Processor Bus Protocol K Shimizu, D Dill, CT Chou Correct Hardware Design and verification Methods, 340-354, 2001 | 30 | 2001 |
| Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols X Chen, Y Yang, G Gopalakrishnan, CT Chou Formal Methods in System Design 36 (1), 37-64, 2010 | 23 | 2010 |
| Hierarchical cache coherence protocol verification one level at a time through assume guarantee X Chen, Y Yang, M Delisi, G Gopalakrishnan, CT Chou 2007 IEEE International High Level Design Validation and Test Workshop, 107-114, 2007 | 23 | 2007 |
| Linear broadcast routing CT Chou, IS Gopal Journal of Algorithms 10 (4), 490-517, 1989 | 23 | 1989 |
| Satisfying memory ordering requirements between partial reads and non-snoop accesses RH Beers, C Chou, RJ Safranek, J Vash US Patent 8,250,311, 2012 | 22 | 2012 |
| Memory system for supporting multiple parallel accesses at very high frequencies HS Ramagopal, MS Chinnakonda, TM Tran US Patent 6,963,962, 2005 | 22 | 2005 |
| Predicates, temporal logic, and simulations CT Chou HOL Users' Group Workshop, 310-323, 1993 | 18 | 1993 |
| SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES RH Beers, CT Chou, RJ Safranek US Patent 8,205,045, 2008 | 15 | 2008 |
Ganesh GopalakrishnanProfessor of Computer Science, University of UtahVerified email at cs.utah.edu
