Standby-power-free integrated circuits using MTJ-based VLSI computing T Hanyu, T Endoh, D Suzuki, H Koike, Y Ma, N Onizawa, M Natsui, ... Proceedings of the IEEE 104 (10), 1844-1863, 2016 | 134 | 2016 |

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array D Suzuki, M Natsui, S Ikeda, H Hasegawa, K Miura, J Hayakawa, T Endoh, ... 2009 Symposium on VLSI Circuits, 80-81, 2009 | 85 | 2009 |

Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... IEEE Journal of Solid-State Circuits 50 (2), 476-489, 2014 | 71 | 2014 |

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions D Suzuki, M Natsui, T Endoh, H Ohno, T Hanyu Journal of Applied Physics 111 (7), 2012 | 71 | 2012 |

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 70 | 2013 |

Cost-efficient self-terminated write driver for spin-transfer-torque RAM and logic D Suzuki, M Natsui, A Mochizuki, T Hanyu IEEE Transactions on Magnetics 50 (11), 1-4, 2014 | 67 | 2014 |

Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control S Matsunaga, A Katsumata, M Natsui, S Fukami, T Endoh, H Ohno, ... 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 298-299, 2011 | 67 | 2011 |

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400° C thermal tolerance by canted SOT structure and its advanced patterning … H Honjo, TVA Nguyen, T Watanabe, T Nasuno, C Zhang, T Tanigawa, ... 2019 IEEE International Electron Devices Meeting (IEDM), 28.5. 1-28.5. 4, 2019 | 64 | 2019 |

A 47.14- 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications M Natsui, D Suzuki, A Tamakoshi, T Watanabe, H Honjo, H Koike, ... IEEE Journal of Solid-State Circuits 54 (11), 2991-3004, 2019 | 56 | 2019 |

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure D Suzuki, M Natsui, A Mochizuki, S Miura, H Honjo, H Sato, S Fukami, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C172-C173, 2015 | 53 | 2015 |

Design of a nine-transistor/two-magnetic-tunnel-junction-cell-based low-energy nonvolatile ternary content-addressable memory S Matsunaga, A Katsumata, M Natsui, T Endoh, H Ohno, T Hanyu Japanese Journal of Applied Physics 51 (2S), 02BM06, 2012 | 48 | 2012 |

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine S Matsunaga, N Sakimura, R Nebashi, Y Tsuji, A Morioka, T Sugibayashi, ... 2013 Symposium on VLSI Technology, C106-C107, 2013 | 44 | 2013 |

A 71%-area-reduced six-input nonvolatile lookup-table circuit using a three-terminal magnetic-tunnel-junction-based single-ended structure D Suzuki, Y Lin, M Natsui, T Hanyu Japanese Journal of Applied Physics 52 (4S), 04CM04, 2013 | 40 | 2013 |

Design optimization of high-speed and low-power operational transconductance amplifier using g m/I D lookup table methodology T Konishi, K Inazu, JG Lee, M Natsui, S Masui, B Murmann IEICE transactions on electronics 94 (3), 334-345, 2011 | 38 | 2011 |

Dual-port SOT-MRAM achieving 90-MHz read and 60-MHz write operations under field-assistance-free condition M Natsui, A Tamakoshi, H Honjo, T Watanabe, T Nasuno, C Zhang, ... IEEE Journal of Solid-State Circuits 56 (4), 1116-1128, 2020 | 34 | 2020 |

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA D Suzuki, M Natsui, T Hanyu 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 31 | 2012 |

Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware M Natsui, T Chiba, T Hanyu Japanese Journal of Applied Physics 58 (SB), SBBB01, 2019 | 30 | 2019 |

Systematic intrusion detection technique for an in-vehicle network based on time-series feature extraction H Suda, M Natsui, T Hanyu 2018 IEEE 48th international symposium on multiple-valued logic (ISMVL), 56-61, 2018 | 30 | 2018 |

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm T Hanyu, D Suzuki, N Onizawa, S Matsunaga, M Natsui, A Mochizuki 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 28 | 2015 |

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications D Suzuki, M Natsui, A Mochizuki, S Miura, H Honjo, K Kinoshita, H Sato, ... IEICE Electronics Express 10 (23), 20130772-20130772, 2013 | 26 | 2013 |