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Tim Baldauf
Tim Baldauf
Scientist, HTW Dresden
Verified email at htw-dresden.de
Title
Cited by
Cited by
Year
Functionality-enhanced logic gate design enabled by symmetrical reconfigurable silicon nanowire transistors
J Trommer, A Heinzig, T Baldauf, S Slesazeck, T Mikolajick, WM Weber
IEEE Transactions on Nanotechnology 14 (4), 689-698, 2015
862015
The RFET—A reconfigurable nanowire transistor and its application to novel electronic circuits and systems
T Mikolajick, A Heinzig, J Trommer, T Baldauf, WM Weber
Semiconductor Science and Technology 32 (4), 043001, 2017
602017
Enabling energy efficiency and polarity control in germanium nanowire transistors by individually gated nanojunctions
J Trommer, A Heinzig, U Muhle, M Löffler, A Winzer, PM Jordan, ...
ACS nano 11 (2), 1704-1711, 2017
602017
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits
J Trommer, A Heinzig, T Baldauf, T Mikolajick, WM Weber, M Raitza, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 169-174, 2016
362016
Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
T Baldauf, T Herrmann, S Flachowsky, R Illgen
US Patent 8,912,606, 2014
342014
Top-down technology for reconfigurable nanowire FETs with symmetric on-currents
M Simon, A Heinzig, J Trommer, T Baldauf, T Mikolajick, WM Weber
IEEE Transactions on Nanotechnology 16 (5), 812-819, 2017
312017
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
S Rai, A Rupani, D Walter, M Raitza, A Heinzig, T Baldauf, J Trommer, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 605-608, 2018
212018
Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors
T Baldauf, A Heinzig, J Trommer, T Mikolajick, WM Weber
Solid-State Electronics 128, 148-154, 2017
212017
Stress-dependent performance optimization of reconfigurable silicon nanowire transistors
T Baldauf, A Heinzig, J Trommer, T Mikolajick, WM Weber
IEEE Electron Device Letters 36 (10), 991-993, 2015
202015
Threshold voltage adjustment in a Fin transistor by corner implantation
T Baldauf, A Wei, T Herrmann, S Flachowsky, R Illgen
US Patent 8,580,643, 2013
202013
A wired-AND transistor: Polarity controllable FET with multiple inputs
M Simon, J Trommer, B Liang, D Fischer, T Baldauf, MB Khan, A Heinzig, ...
2018 76th Device Research Conference (DRC), 1-2, 2018
152018
Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized?
S Flachowsky, R Illgen, T Herrmann, T Baldauf, A Wei, J Höntschel, W Klix, ...
International Conference on Ultimate Integration on Silicon ULIS (Glasgow …, 2010
152010
Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform
M Simon, A Heinzig, J Trommer, T Baldauf, T Mikolajick, WM Weber
2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-3, 2016
142016
Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors
T Baldauf, A Heinzig, T Mikolajick, WM Weber, J Trommer
2016 Joint International EUROSOI Workshop and International Conference on …, 2016
102016
Method of forming a semiconductor structure including a vertical nanowire
T Baldauf, S Flachowsky, T Hermann, R Illgen
US Patent 8,835,255, 2014
82014
Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process
T Baldauf, A Wei, R Illgen, S Flachowsky, T Herrmann, J Höntschel, ...
2011 International Semiconductor Device Research Symposium (ISDRS), 1-2, 2011
62011
Simulation and optimization of tri-gates in a 22 nm hybrid tri-gate/planar process
T Baldauf, A Wei, R Illgen, S Flachowsky, T Herrmann, T Feudel, ...
Ulis 2011 Ultimate Integration on Silicon, 1-4, 2011
62011
Reconfigurable nanowire field effect transistor, a nanowire array and an integrated circuit thereof
T Baldauf, A Heinzig, WM Weber
US Patent 10,347,760, 2019
42019
Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits
J Trommer, S Slesazeck, WM Weber, A Heinzig, T Baldauf, T Mikolajick
EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and …, 2015
42015
Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process
T Baldauf, A Wei, T Herrmann, S Flachowsky, R Illgen, J Höntschel, ...
2011 Semiconductor Conference Dresden, 1-4, 2011
42011
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