Maciej Ciesielski
Maciej Ciesielski
Professor of ELectrical and Computer Engineering
Bestätigte E-Mail-Adresse bei ecs.umass.edu
Titel
Zitiert von
Zitiert von
Jahr
BDS: A BDD-based logic optimization system
C Yang, M Ciesielski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
3102002
Wave-pipelining: A tutorial and research survey
WP Burleson, M Ciesielski, F Klass, W Liu
IEEE Transactions on very large scale integration (vlsi) systems 6 (3), 464-474, 1998
2801998
Logic synthesis and verification
S Hassoun, T Sasao
Springer Science & Business Media, 2012
1952012
Logic synthesis and verification
S Hassoun, T Sasao
Springer Science & Business Media, 2012
1952012
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
S Yang, MJ Ciesielski
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1991
1151991
LPSAT: A unified approach to RTL satisfiability
Z Zeng, P Kalla, M Ciesielski
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
1072001
Taylor expansion diagrams: A canonical representation for verification of data flow designs
M Ciesielski, P Kalla, S Askar
IEEE Transactions on Computers 55 (9), 1188-1201, 2006
802006
Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification
MJ Ciesielski, P Kalla, Z Zheng, B Rouzeyre
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
762002
Verification of gate-level arithmetic circuits by function extraction
M Ciesielski, C Yu, W Brown, D Liu, A Rossi
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
702015
PLADE: A two-stage PLA decomposition
MJ Ciesielski, S Yang
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1992
671992
Incremental SAT-based reverse engineering of camouflaged logic circuits
C Yu, X Zhang, D Liu, M Ciesielski, D Holcomb
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
582017
Clock period minimization with wave pipelining
DA Joy, MJ Ciesielski
IEEE transactions on computer-aided design of integrated circuits and …, 1993
511993
An optimum layer assignment for routing in ICs and PCBs
MJ Ciesielski, E Kinnen
18th Design Automation Conference, 733-737, 1981
501981
BDD decomposition for efficient logic synthesis
C Yang, V Singhal, M Ciesielski
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999
491999
Functional test generation using constraint logic programming
Z Zeng, MJ Ciesielski, B Rouzeyre
11th International Conference on VLSI/SOC, 375-387, 2002
432002
Multiple-valued Boolean minimization based on graph coloring
MJ Ciesielski, S Yang, MA Perkowski
Proceedings 1989 IEEE International Conference on Computer Design: VLSI in …, 1989
431989
Formal verification of arithmetic circuits by function extraction
C Yu, W Brown, D Liu, A Rossi, M Ciesielski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
372016
Placement for clock period minimization with multiple wave propagation
DA Joy, MJ Ciesielski
Proceedings of the 28th ACM/IEEE Design automation conference, 640-643, 1991
351991
Practical design verification
DK Pradhan, IG Harris
Cambridge University Press, 2009
342009
A comprehensive approach to the partial scan problem using implicit state enumeration
P Kalla, M Ciesielski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
302002
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