Matthias Gries
Matthias Gries
Huawei Technologies, European Research Center
Bestätigte E-Mail-Adresse bei - Startseite
TitelZitiert vonJahr
A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ...
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 …, 2010
A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling
J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ...
IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2011
Methods for evaluating and covering the design space during early design development
M Gries
Integration, the VLSI journal 38 (2), 131-183, 2004
Design space exploration of network processor architectures
L Thiele, S Chakraborty, M Gries, S Künzli
In Network Processor Design: Issues and Practices, Volume 1, 2002
A framework for evaluating design tradeoffs in packet processing architectures
L Thiele, S Chakraborty, M Gries, S Künzli
Proceedings of the 39th annual Design Automation Conference, 880-885, 2002
Building ASIPs: The Mescal Methodology
M Gries, K Keutzer
Springer Science & Business Media, 2006
Embedded software in network processors—models and algorithms
L Thiele, S Chakraborty, M Gries, A Maxiaguine, J Greutert
International Workshop on Embedded Software, 416-434, 2001
FunState-an internal design representation for codesign
K Strehl, L Thiele, M Gries, D Ziegenbein, R Ernst, J Teich
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (4), 524-544, 2001
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores
A Bartolini, M Cacciari, A Tilli, L Benini, M Gries
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 311-316, 2010
Comparing analytical modeling with simulation for network processors: A case study
M Gries, C Kulkarni, C Sauer, K Keutzer
Proceedings of the conference on Design, Automation and Test in Europe …, 2003
Adaptive address mapping with dynamic runtime memory mapping selection
A Schaefer, M Gries
US Patent 8,135,936, 2012
Phase-based application-driven hierarchical power management on the single-chip cloud computer
N Ioannou, M Kauschke, M Gries, M Cintra
Parallel Architectures and Compilation Techniques (PACT), 2011 International …, 2011
Exploring trade-offs in performance and programmability of processing element topologies for network processors
M Gries, C Kulkarni, C Sauer, K Keutzer
Network Processor Design: Issues and Practices 2, 1-5, 2003
SCC: A flexible architecture for many-core platform research
M Gries, U Hoffmann, M Konow, M Riepen
Computing in Science & Engineering 13 (6), 79-83, 2011
Programming challenges in network processor deployment
C Kulkarni, M Gries, C Sauer, K Keutzer
Proceedings of the 2003 international conference on Compilers, architecture …, 2003
LMS-based low-complexity game workload prediction for DVFS
B Dietrich, S Nunna, D Goswami, S Chakraborty, M Gries
Computer Design (ICCD), 2010 IEEE International Conference on, 417-424, 2010
The impact of recent DRAM architectures on embedded systems performance
M Gries
Euromicro Conference, 2000. Proceedings of the 26th 1, 282-289, 2000
3D memory configurable for performance and power
R Saraswat, M Gries
US Patent 8,737,108, 2014
Algorithm-architecture trade-offs in network processor design
M Gries
Technische Informatik 41, 2001
Dynamic operations for 3D stacked memory using thermal data
R Saraswat, M Gries
US Patent 9,195,577, 2015
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