| A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010 | 741 | 2010 |
| A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ... IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010 | 427 | 2010 |
| Methods for evaluating and covering the design space during early design development M Gries Integration, the VLSI journal 38 (2), 131-183, 2004 | 339 | 2004 |
| Design space exploration of network processor architectures L Thiele, S Chakraborty, M Gries, S Künzli Network Processor Design: Issues and Practices 1, 55-89, 2002 | 184 | 2002 |
| A framework for evaluating design tradeoffs in packet processing architectures L Thiele, S Chakraborty, M Gries, S Kunzli Proceedings 2002 Design Automation Conference (IEEE Cat. No. 02CH37324), 880-885, 2002 | 121 | 2002 |
| Building ASIPs: The Mescal Methodology M Gries, K Keutzer Springer Science & Business Media, 2006 | 92 | 2006 |
| Embedded software in network processors—models and algorithms L Thiele, S Chakraborty, M Gries, A Maxiaguine, J Greutert International Workshop on Embedded Software, 416-434, 2001 | 92 | 2001 |
| FunState-an internal design representation for codesign K Strehl, L Thiele, M Gries, D Ziegenbein, R Ernst, J Teich IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (4), 524-544, 2001 | 87 | 2001 |
| A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores A Bartolini, M Cacciari, A Tilli, L Benini, M Gries Proceedings of the 20th symposium on Great lakes symposium on VLSI, 311-316, 2010 | 72 | 2010 |
| Adaptive address mapping with dynamic runtime memory mapping selection A Schaefer, M Gries US Patent 8,135,936, 2012 | 61 | 2012 |
| Phase-based application-driven hierarchical power management on the single-chip cloud computer N Ioannou, M Kauschke, M Gries, M Cintra 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 54 | 2011 |
| Comparing analytical modeling with simulation for network processors: A case study M Gries, C Kulkarni, C Sauer, K Keutzer Proceedings of the conference on Design, Automation and Test in Europe …, 2003 | 54 | 2003 |
| Exploring trade-offs in performance and programmability of processing element topologies for network processors M Gries, C Kulkarni, C Sauer, K Keutzer Network Processor Design: Issues and Practices 2, 1-5, 2003 | 39 | 2003 |
| SCC: A flexible architecture for many-core platform research M Gries, U Hoffmann, M Konow, M Riepen Computing in Science & Engineering 13 (6), 79, 2011 | 37 | 2011 |
| Programming challenges in network processor deployment C Kulkarni, M Gries, C Sauer, K Keutzer Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 33 | 2003 |
| LMS-based low-complexity game workload prediction for DVFS B Dietrich, S Nunna, D Goswami, S Chakraborty, M Gries 2010 IEEE International Conference on Computer Design, 417-424, 2010 | 27 | 2010 |
| Dynamic operations for 3D stacked memory using thermal data R Saraswat, M Gries US Patent 9,195,577, 2015 | 26 | 2015 |
| Adaptive address mapping with dynamic runtime memory mapping selection A Schaefer, M Gries US Patent 9,026,767, 2015 | 26 | 2015 |
| 3D memory configurable for performance and power R Saraswat, M Gries US Patent 8,737,108, 2014 | 25 | 2014 |
| The impact of recent DRAM architectures on embedded systems performance M Gries Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics …, 2000 | 23 | 2000 |
Samarjit ChakrabortyProfessor of Electrical Engineering, TU Munich, GermanyVerified email at tum.de