Matthias Gries
Matthias Gries
Huawei Technologies, Munich Research Center
Bestätigte E-Mail-Adresse bei - Startseite
Zitiert von
Zitiert von
A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010
A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling
J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ...
IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010
Methods for evaluating and covering the design space during early design development
M Gries
Integration 38 (2), 131-183, 2004
4 Design Space Exploration of Network Processor
L Thiele, S Chakraborty, M Gries, S Kunzli
Network Processor Design: Issues and Practices 1, 2003
A framework for evaluating design tradeoffs in packet processing architectures
L Thiele, S Chakraborty, M Gries, S Künzli
Proceedings of the 39th annual Design Automation Conference, 880-885, 2002
Building ASIPS: The mescal methodology
M Gries, K Keutzer
Springer Science & Business Media, 2005
Embedded software in network processors—models and algorithms
L Thiele, S Chakraborty, M Gries, A Maxiaguine, J Greutert
Embedded Software: First International Workshop, EMSOFT 2001 Tahoe City, CA …, 2001
FunState-an internal design representation for codesign
K Strehl, L Thiele, M Gries, D Ziegenbein, R Ernst, J Teich
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (4), 524-544, 2001
Adaptive address mapping with dynamic runtime memory mapping selection
A Schaefer, M Gries
US Patent 8,135,936, 2012
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores
A Bartolini, M Cacciari, A Tilli, L Benini, M Gries
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 311-316, 2010
Phase-based application-driven hierarchical power management on the single-chip cloud computer
N Ioannou, M Kauschke, M Gries, M Cintra
2011 International Conference on Parallel Architectures and Compilation …, 2011
Comparing analytical modeling with simulation for network processors: A case study
M Gries, C Kulkarni, C Sauer, K Keutzer
2003 Design, Automation and Test in Europe Conference and Exhibition, 256 …, 2003
SCC: A Flexible Architecture for Many-Core Platform Research.
M Gries, U Hoffmann, M Konow, M Riepen
Comput. Sci. Eng. 13 (6), 79-83, 2011
3D memory configurable for performance and power
R Saraswat, M Gries
US Patent 8,737,108, 2014
Exploring trade-offs in performance and programmability of processing element topologies for network processors
M Gries, C Kulkarni, C Sauer, K Keutzer
Network Processor Design: Issues and Practices 2, 1-5, 2003
Dynamic operations for 3D stacked memory using thermal data
R Saraswat, M Gries
US Patent 9,195,577, 2015
Design space exploration of network processor architectures
L Thiele, S Chakraborty, M Gries, S Künzli
Network Processor Design: Issues and Practices 1, 2002
LMS-based low-complexity game workload prediction for DVFS
B Dietrich, S Nunna, D Goswami, S Chakraborty, M Gries
2010 IEEE International Conference on Computer Design, 417-424, 2010
Programming challenges in network processor deployment
C Kulkarni, M Gries, C Sauer, K Keutzer
Proceedings of the 2003 international conference on Compilers, architecture …, 2003
Heterogenous memory access
R Saraswat, M Gries, NP Cowley
US Patent 9,513,692, 2016
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