| A score-based classification method for identifying hardware-trojans at gate-level netlists M Oya, Y Shi, M Yanagisawa, N Togawa 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 465-470, 2015 | 136 | 2015 |
| Dynamically changeable secure scan architecture against scan-based side channel attack Y Atobe, Y Shi, M Yanagisawa, N Togawa 2012 International SoC Design Conference (ISOCC), 155-158, 2012 | 56 | 2012 |
| Hardware trojan detection utilizing machine learning approaches K Hasegawa, Y Shi, N Togawa 2018 17th IEEE International Conference On Trust, Security And Privacy In …, 2018 | 39 | 2018 |
| Secure scan design with dynamically configurable connection Y Atobe, Y Shi, M Yanagisawa, N Togawa 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing …, 2013 | 37 | 2013 |
| Robust secure scan design against scan-based differential cryptanalysis Y Shi, N Togawa, M Yanagisawa, T Ohtsuki IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 176-181, 2011 | 31 | 2011 |
| MH4: multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures S Abe, Y Shi, M Yanagisawa, N Togawa IEICE Electronics Express 9 (17), 1414-1422, 2012 | 24 | 2012 |
| Suspicious timing error prediction with in-cycle clock gating Y Shi, H Igarashi, N Togawa, M Yanagisawa International Symposium on Quality Electronic Design (ISQED), 335-340, 2013 | 22 | 2013 |
| Low power test compression technique for designs with multiple scan chain Y Shi, N Togawa, M Yanagisawa, T Ohtsuki, S Kimura 14th Asian Test Symposium (ATS'05), 386-389, 2005 | 20 | 2005 |
| Transition detector-based radiation-hardened latch for both single-and multiple-node upsets S Tajima, M Yanagisawa, Y Shi IEEE transactions on circuits and systems II: express briefs 67 (6), 1114-1118, 2019 | 19 | 2019 |
| Concurrent faulty clock detection for crypto circuits against clock glitch based DFA H Igarashi, Y Shi, M Yanagisawa, N Togawa 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1432-1435, 2013 | 18 | 2013 |
| FCSCAN: An efficient multiscan-based test compression technique for test cost reduction Y Shi, N Togawa, S Kimura, M Yanagisawa, T Ohtsuki Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 18 | 2006 |
| FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension Y Wang, Y Shi, C Wang, Y Ha 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 17 | 2015 |
| State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit Y Atobe, Y Shi, M Yanagisawa, N Togawa 2012 IEEE Asia Pacific Conference on Circuits and Systems, 607-610, 2012 | 17 | 2012 |
| State-dependent changeable scan architecture against scan-based side channel attacks R Nara, H Atobe, Y Shi, N Togawa, M Yanagisawa, T Ohtsuki Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 16 | 2010 |
| A new low power BIST methodology by altering the structure of linear feedback shift registers R Li, C Hu, J Yang, Z Zhang, Y Shi, L Shi ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No …, 2001 | 13 | 2001 |
| In-situ Trojan authentication for invalidating hardware-Trojan functions M Oya, Y Shi, M Yanagisawa, N Togawa 2016 17th International Symposium on Quality Electronic Design (ISQED), 152-157, 2016 | 12 | 2016 |
| A hardware-Trojans identifying method based on Trojan net scoring at gate-level netlists M Oya, Y Shi, N Yamashita, T Okamura, Y Tsunoo, S Goto, M Yanagisawa, ... IEICE Transactions on fundamentals of electronics, communications and …, 2015 | 12 | 2015 |
| Multiple test set generation method for LFSR-based BIST Y Shi, Z Zhang Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 12 | 2003 |
| Design-for-secure-test for crypto cores Y Shi, N Togawa, M Yanagisawa, T Ohtsuki 2009 International Test Conference, 1-1, 2009 | 11 | 2009 |
| Design for secure test-a case study on pipelined advanced encryption standard Y Shi, N Togawa, M Yanagisawa, T Ohtsuki 2007 IEEE International Symposium on Circuits and Systems, 149-152, 2007 | 9 | 2007 |
