paolo madoglio
paolo madoglio
Verified email at intel.com
Title
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Year
A 2.4-GHz 20–40-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS
A Ravi, P Madoglio, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ...
IEEE Journal of Solid-State Circuits 47 (12), 3184-3196, 2012
852012
Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL
M Zanuso, P Madoglio, S Levantino, C Samori, AL Lacaita
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 548-555, 2009
612009
Digital delay-locked loop with drift sensor
S Pellerano, P Madoglio
US Patent 8,598,930, 2013
512013
A 4.75-GHz fractional frequency divider-by-1.25 with TDC-based all-digital spur calibration in 45-nm CMOS
S Pellerano, P Madoglio, Y Palaskas
IEEE Journal of Solid-State Circuits 44 (12), 3422-3433, 2009
512009
A 20dBm 2.4 GHz digital outphasing transmitter for WLAN application in 32nm CMOS
P Madoglio, A Ravi, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ...
2012 IEEE International Solid-State Circuits Conference, 168-170, 2012
482012
Quantization effects in all-digital phase-locked loops
P Madoglio, M Zanuso, S Levantino, C Samori, AL Lacaita
IEEE Transactions on Circuits and Systems II: Express Briefs 54 (12), 1120-1124, 2007
462007
13.6 A 2.4 GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications
P Madoglio, H Xu, K Chandrashekar, L Cuellar, M Faisal, WY Li, HS Kim, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 226-227, 2017
372017
Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter
A Ravi, O Degani, HS Kim, H Lakdawala, YW Li, P Madoglio
US Patent 8,390,349, 2013
252013
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management
K Chandrashekar, S Pellerano, P Madoglio, A Ravi, Y Palaskas
2012 IEEE International Solid-State Circuits Conference, 352-354, 2012
212012
A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique
HS Kim, C Ornelas, K Chandrashekar, D Shi, P Su, P Madoglio, WY Li, ...
IEEE journal of solid-state circuits 48 (7), 1721-1729, 2013
192013
A 2.5 GHz delay-based wideband OFDM outphasing modulator in 45nm-LP CMOS
A Ravi, P Madoglio, M Verhelst, M Sajadieh, M Aguirre, H Xu, S Pellerano, ...
2011 Symposium on VLSI Circuits-Digest of Technical Papers, 26-27, 2011
192011
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ modulator based on standard cell design with time-interleaving
P Madoglio, A Ravi, L Cuellar, S Pellerano, P Seddighrad, I Lomeli, ...
IEEE Journal of Solid-State Circuits 45 (7), 1410-1420, 2010
192010
Segmented digital-to-time converter calibration
G Palaskas, P Madoglio, S Pellerano, A Ravi, K Chandrashekar
US Patent 9,209,958, 2015
172015
System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband RF outphasing/polar transmitters
A Ravi, P Madoglio, M Verhelst, G Palaskas
US Patent 8,222,966, 2012
162012
Digital phase lock loop
A Ravi, PE Su, P Madoglio, G Palaskas
US Patent 8,207,770, 2012
152012
A 4.75 GHz fractional frequency divider with digital spur calibration in 45nm CMOS
S Pellerano, P Madoglio, Y Palaskas
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
92009
Parallel digital-to-time converter architecture
P Madoglio, S Pellerano
US Patent 9,054,925, 2015
82015
Redundant delay digital-to-time converter
S Henzler, M Schimper, P Madoglio, S Pellerano, K Chandrashekar
US Patent 9,130,588, 2015
72015
Dynamic element matching for time-to-digital converters
S Pellerano, P Madoglio, A Ravi
US Patent 8,198,929, 2012
72012
Delay element array for time-to-digital converters
P Madoglio, S Pellerano
US Patent 7,782,104, 2010
72010
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