Josep Torrellas
Josep Torrellas
Professor of Computer Science, University of Illinois Urbana-Champaign
Bestätigte E-Mail-Adresse bei illinois.edu - Startseite
Titel
Zitiert von
Zitiert von
Jahr
VARIUS: A model of process variation and resulting timing errors for microarchitects
SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas
IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008
4712008
A chip-multiprocessor architecture with speculative multithreading
V Krishnan, J Torrellas
IEEE Transactions on Computers 48 (9), 866-880, 1999
4211999
Variation-aware application scheduling and power management for chip multiprocessors
R Teodorescu, J Torrellas
ACM SIGARCH computer architecture news 36 (3), 363-374, 2008
4082008
Bulk disambiguation of speculative threads in multiprocessors
L Ceze, J Tuck, J Torrellas, C Cascaval
ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006
4072006
ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors
M Prvulovic, Z Zhang, J Torrellas
ACM SIGARCH Computer Architecture News 30 (2), 111-122, 2002
3392002
FlexRAM: Toward an advanced intelligent memory system
Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999
3171999
FlexRAM: Toward an advanced intelligent memory system
Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas
Computer Design (ICCD), 1999 IEEE International Conference on, 5-14, 1999
3171999
POSH: a TLS compiler that exploits program structure
W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
3092006
False sharing and spatial locality in multiprocessor caches
J Torrellas, HS Lam, JL Hennessy
IEEE Transactions on Computers 43 (6), 651-663, 1994
3061994
Proving program termination
B Cook, A Podelski, A Rybalchenko
Communications of the ACM 54 (5), 88-98, 2011
300*2011
Characterizing and predicting program behavior and its variability
E Duesterwald, C Cascaval, S Dwarkadas
2003 12th International Conference on Parallel Architectures and Compilation …, 2003
3002003
BulkSC: Bulk enforcement of sequential consistency
L Ceze, J Tuck, P Montesinos, J Torrellas
Proceedings of the 34th annual international symposium on Computer …, 2007
2972007
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
J Martínez, J Renau, M Huang, M Prvulovic, J Torrellas
Intl. Symp. on Microarchitecture (MICRO), 2002
2912002
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
M Cintra, JF Martínez, J Torrellas
Proceedings of the 27th annual international symposium on Computer …, 2000
2772000
Facelift: Hiding and slowing down aging in multicores
A Tiwari, J Torrellas
2008 41st IEEE/ACM International Symposium on Microarchitecture, 129-140, 2008
2752008
Delorean: Recording and deterministically replaying shared-memory multiprocessor execution ef? ciently
P Montesinos, L Ceze, J Torrellas
ACM SIGARCH Computer Architecture News 36 (3), 289-300, 2008
2652008
Speculative synchronization: Applying thread-level speculation to explicitly parallel applications
JF Martinez, J Torrellas
ACM SIGOPS Operating Systems Review 36 (5), 18-29, 2002
2562002
Positional adaptation of processors: application to energy reduction
MC Huang, J Renau, J Torrellas
30th Annual International Symposium on Computer Architecture, 2003 …, 2003
2502003
A framework for dynamic energy efficiency and temperature management
M Huang, J Renau, SM Yoo, J Torrellas
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
2152000
Using a user-level memory thread for correlation prefetching
Y Solihin, J Lee, J Torrellas
Proceedings 29th Annual International Symposium on Computer Architecture …, 2002
2042002
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