Robert Mullins
Robert Mullins
Computer Laboratory, University of Cambridge
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Zitiert von
Zitiert von
Low-latency virtual-channel routers for on-chip networks
R Mullins, A West, S Moore
Proceedings. 31st Annual International Symposium on Computer Architecture …, 2004
Improving smart card security using self-timed circuits
S Moore, R Anderson, P Cunningham, R Mullins, G Taylor
Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002
Point to point GALS interconnect
S Moore, G Taylor, R Mullins, P Robinson
Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International …, 2002
The design and implementation of a low-latency on-chip network
R Mullins, A West, S Moore
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
A power and energy exploration of network-on-chip architectures
A Banerjee, R Mullins, S Moore
First International Symposium on Networks-on-Chip (NOCS'07), 163-172, 2007
Security evaluation of asynchronous circuits
JJA Fournier, S Moore, H Li, R Mullins, G Taylor
International Workshop on Cryptographic Hardware and Embedded Systems, 137-151, 2003
Balanced self-checking asynchronous logic for smart card applications
S Moore, R Anderson, R Mullins, G Taylor, JJA Fournier
Microprocessors and Microsystems 27 (9), 421-430, 2003
Self calibrating clocks for globally asynchronous locally synchronous systems
SW Moore, GS Taylor, PA Cunningham, RD Mullins, P Robinson
Proceedings 2000 International Conference on Computer Design, 73-78, 2000
Demystifying data-driven and pausible clocking schemes
R Mullins, S Moore
13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007
An energy and performance exploration of network-on-chip architectures
A Banerjee, PT Wolkotte, RD Mullins, SW Moore, GJM Smit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 319-329, 2009
Dynamic channel pruning: Feature boosting and suppression
X Gao, Y Zhao, Ł Dudziak, R Mullins, C Xu
ICLR 2019, 2018
Commodity single board computer clusters and their applications
SJ Johnston, PJ Basford, CS Perkins, H Herry, FP Tso, D Pezaros, ...
Future Generation Computer Systems, 2018
Minimising dynamic power consumption in on-chip networks
R Mullins
2006 International Symposium on System-on-Chip, 1-4, 2006
Using stoppable clocks to safely interface asynchronous and synchronous subsystems
SW Moore, GS Taylor, PA Cunningham, RD Mullins, P Robinson
AINT (Asynchronous INTerfaces) Workshop, Delft, Netherlands, 2000
To compress or not to compress: Understanding the interactions between adversarial attacks and neural network compression
Y Zhao, I Shumailov, R Mullins, R Anderson
arXiv preprint arXiv:1810.00208, 2018
On the reduction of computational complexity of deep convolutional neural networks
P Maji, R Mullins
Entropy 20 (4), 305, 2018
Micronets: A model for decentralising control in asynchronous processor architectures
DK Arvind, RD Mullins, VEF Rebello
Proceedings Second Working Conference on Asynchronous Design Methodologies …, 1995
A network of time-division multiplexed wiring for FPGAs
R Francis, S Moore, R Mullins
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 35-44, 2008
Performance implications of transient loop-carried data dependences in automatically parallelized loops
N Murphy, T Jones, R Mullins, S Campanoni
Proceedings of the 25th International Conference on Compiler Construction, 23-33, 2016
Designing a physical locality aware coherence protocol for chip-multiprocessors
C Fensch, N Barrow-Williams, RD Mullins, S Moore
IEEE Transactions on Computers 62 (5), 914-928, 2012
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