Daniel Ziener

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Jürgen TeichFull Professor, Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergVerified email at cs.fau.de
Dirk KochSchool of Computer Science, University of ManchesterVerified email at recobus.de
Stefan WildermannFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)Verified email at fau.de
Frank HannigFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)Verified email at cs.fau.de
Klaus Meyer-WegenerProfessor of Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergVerified email at fau.de
Jorge EchavarriaFriedrich-Alexander Universität Erlangen-NürnbergVerified email at fau.de
Robért GleinFPGA Expert (SAR) at Capella SpaceVerified email at colorado.edu
Florian RittnerVerified email at fau.de
Felix ReimannAudi Electronics Venture GmbHVerified email at fex-it.de
Norbert WehnUniversity of KaiserslauternVerified email at eit.uni-kl.de
Andreas HerkersdorfProfessor for Electrical and Computer EngineeringVerified email at tum.de
Jim TorresenProfessor University of OsloVerified email at ifi.uio.no
Michael GlaßProfessor at Ulm UniversityVerified email at uni-ulm.de
Rolf ErnstProfessor at Institute of Computer and Network Engineering, TU Braunschweig, GermanyVerified email at tu-bs.de
Oliver BringmannProfessor of Embedded Systems, Eberhard Karls Universität Tübingen, GermanyVerified email at uni-tuebingen.de
Andreas WeichslgartnerCARIAD SEVerified email at cariad.technology
Kimon KarrasAMDVerified email at amd.com
Michaela BlottAMD ResearchVerified email at amd.com
Peter AthanasEmeritus Professor of Electrical and Computer EngineeringVerified email at vt.edu
Ingrid VerbauwhedeKU LeuvenVerified email at esat.kuleuven.be

Daniel Ziener

Professor for Computer Architecture and Embedded Systems, Technische Universität Ilmenau

Verified email at tu-ilmenau.de - Homepage

Reconfigurable Computing FPGA Embedded Systems Reliability Security


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On-the-fly composition of FPGA-based SQL query accelerators using a partially reconfigurable module library C Dennl, D Ziener, J Teich 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012	105	2012
FPGAs for software programmers D Koch, F Hannig, D Ziener Springer, 2016	98	2016
Power signature watermarking of IP cores for FPGAs D Ziener, J Teich Journal of Signal Processing Systems 51, 123-136, 2008	94	2008
Acceleration of SQL restrictions and aggregations through FPGA-based dynamic partial reconfiguration C Dennl, D Ziener, J Teich 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013	71	2013
Identifying FPGA IP-cores based on lookup table content analysis D Ziener, S Aßmus, J Teich 2006 international conference on field programmable logic and applications, 1-6, 2006	71	2006
FPGA-based dynamically reconfigurable SQL query processing D Ziener, F Bauer, A Becher, C Dennl, K Meyer-Wegener, U Schürfeld, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (4), 1-24, 2016	69	2016
Netlist-level IP protection by watermarking for LUT-based FPGAs M Schmid, D Ziener, J Teich 2008 International Conference on Field-Programmable Technology, 209-216, 2008	69	2008
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration A Becher, F Bauer, D Ziener, J Teich 2014 24th International Conference on Field Programmable Logic and …, 2014	60	2014
Partial reconfiguration on FPGAs in practice—Tools and applications D Koch, J Torresen, C Beckhoff, D Ziener, C Dennl, V Breuer, J Teich, ... ARCS 2012, 1-12, 2012	58	2012
A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor R Glein, B Schmidt, F Rittner, J Teich, D Ziener 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014	48	2014
A co-design approach for accelerated SQL query processing via FPGA-based data filtering A Becher, D Ziener, K Meyer-Wegener, J Teich 2015 International Conference on Field Programmable Technology (FPT), 192-195, 2015	45	2015
Using the power side channel of FPGAs for communication D Ziener, F Baueregger, J Teich 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010	37	2010
FPGA core watermarking based on power signature analysis D Ziener, J Teich 2006 IEEE International Conference on Field Programmable Technology, 205-212, 2006	33	2006
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy R Glein, F Rittner, A Becher, D Ziener, J Frickel, J Teich, A Heuberger 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2015	30	2015
Throughput optimizations for FPGA-based deep neural network inference T Posewsky, D Ziener Microprocessors and microsystems 60, 151-161, 2018	29	2018
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs J Echavarria, S Wildermann, A Becher, J Teich, D Ziener 2016 International Conference on Field-Programmable Technology (FPT), 213-216, 2016	28	2016
Symbolic design space exploration for multi-mode reconfigurable systems S Wildermann, F Reimann, D Ziener, J Teich Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011	28	2011
A dynamic reconfigurable architecture for hybrid spiking and convolutional fpga-based neural network designs H Irmak, F Corradi, P Detterer, N Alachiotis, D Ziener Journal of Low Power Electronics and Applications 11 (3), 32, 2021	27	2021
Stress-aware module placement on reconfigurable devices J Angermeier, D Ziener, M Glaß, J Teich 2011 21st International Conference on Field Programmable Logic and …, 2011	27	2011
Increasing flexibility of FPGA-based CNN accelerators with dynamic partial reconfiguration H Irmak, D Ziener, N Alachiotis 2021 31st International Conference on Field-Programmable Logic and …, 2021	25	2021

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